H01L2224/29318

Electrical Interconnect Structure with Radial Spokes for Improved Solder Void Control

An electrical interconnect structure includes a bond pad having a substantially planar bonding surface, and a solder enhancing structure that is disposed on the bonding surface and includes a plurality of raised spokes that are each elevated from the bonding surface. Each of the raised spokes has a lower wettability relative to a liquefied solder material than the bonding surface. Each of the raised spokes extend radially outward from a center of the solder enhancing structure.

ELECTRONIC APPARATUS AND MANUFACTURING METHOD THEREOF
20210233855 · 2021-07-29 · ·

An electronic device includes a first part, and a circuit plate including a circuit substrate, a plating film made of a plating material and being disposed on a front surface of the substrate. The plating film includes a first part region on which the first part is disposed via a first solder, and a liquid-repellent region extending along a periphery side of the first part region in a surface layer of the plating film, and having a liquid repellency greater than a liquid repellency of the plating film. The liquid-repellent region includes a resist region. The plating film includes a remaining portion between the liquid-repellent region and the front surface of the circuit substrate in a thickness direction of the plating film orthogonal to the front surface. The remaining portion is made of the plating material and is free of the oxidized plating material.

ELECTRONIC APPARATUS AND MANUFACTURING METHOD THEREOF
20210233855 · 2021-07-29 · ·

An electronic device includes a first part, and a circuit plate including a circuit substrate, a plating film made of a plating material and being disposed on a front surface of the substrate. The plating film includes a first part region on which the first part is disposed via a first solder, and a liquid-repellent region extending along a periphery side of the first part region in a surface layer of the plating film, and having a liquid repellency greater than a liquid repellency of the plating film. The liquid-repellent region includes a resist region. The plating film includes a remaining portion between the liquid-repellent region and the front surface of the circuit substrate in a thickness direction of the plating film orthogonal to the front surface. The remaining portion is made of the plating material and is free of the oxidized plating material.

Metallic sintered bonding body and die bonding method

A metal sintered bonding body bonds a substrate and a die. In the metal sintered bonding body, at least a center part and corner part of a rectangular region where the metal sintered bonding body faces the die have a low-porosity region whose porosity is lower than an average porosity of the rectangular region. The low-porosity region is located within a strip-shaped region whose central lines are diagonal lines of the rectangular region.

Metallic sintered bonding body and die bonding method

A metal sintered bonding body bonds a substrate and a die. In the metal sintered bonding body, at least a center part and corner part of a rectangular region where the metal sintered bonding body faces the die have a low-porosity region whose porosity is lower than an average porosity of the rectangular region. The low-porosity region is located within a strip-shaped region whose central lines are diagonal lines of the rectangular region.

Information handling system low form factor interface thermal management

Information handling system thermal rejection of thermal energy generated by one or more components, such as a central processing unit and graphics processing unit, is enhanced by disposing boron arsenide between the one or more components and a heat transfer structure that directs thermal energy from the one or more components to a heat rejection region, such as cooling fan exhaust. For instance, the boron arsenide is a layer formed with chemical vapor deposition on a copper heat pipe or a layer of thermal grease infused with the boron arsenide.

TIN OR TIN-ALLOY PLATING LIQUID, BUMP FORMING METHOD, AND CIRCUIT BOARD PRODUCTION METHOD

This tin or tin-alloy plating liquid contains (A) a soluble salt including at least a stannous salt; (B) an acid selected from an organic acid and an inorganic acid, or a salt thereof; (C) a surfactant; (D) a leveling agent; and (E) an additive, wherein the surfactant is a compound (C1) represented by Formula (1) and/or a compound (C2) represented by Formula (2).

##STR00001##

In Formulas (1) and (2), R is an alkyl group having 7 to 13 carbon atoms, m is 5 to 11, n is 1 to 3, and m and n are different from each other.

TIN OR TIN-ALLOY PLATING LIQUID, BUMP FORMING METHOD, AND CIRCUIT BOARD PRODUCTION METHOD

This tin or tin-alloy plating liquid contains (A) a soluble salt including at least a stannous salt; (B) an acid selected from an organic acid and an inorganic acid, or a salt thereof; (C) a surfactant; (D) a leveling agent; and (E) an additive, wherein the surfactant is a compound (C1) represented by Formula (1) and/or a compound (C2) represented by Formula (2).

##STR00001##

In Formulas (1) and (2), R is an alkyl group having 7 to 13 carbon atoms, m is 5 to 11, n is 1 to 3, and m and n are different from each other.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
20210066234 · 2021-03-04 ·

A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
20210066234 · 2021-03-04 ·

A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.