A semiconductor device includes: a semiconductor chip; a case having a frame portion that has an inner wall portion surrounding an housing area in which the semiconductor chip is disposed; a buffer member provided on at last part of the inner wall portion of the case on a side of the housing area; a low expansion member provided on said at least part of the inner wall portion with the buffer member interposed therebetween on the side of the housing area; and a sealing member that seals the housing area, wherein the buffer member has a smaller elastic modulus than the case and the sealing member, and wherein the low expansion member has a smaller linear expansion coefficient than the case and the sealing member.

A semiconductor device includes: a semiconductor chip; a case having a frame portion that has an inner wall portion surrounding an housing area in which the semiconductor chip is disposed; a buffer member provided on at last part of the inner wall portion of the case on a side of the housing area; a low expansion member provided on said at least part of the inner wall portion with the buffer member interposed therebetween on the side of the housing area; and a sealing member that seals the housing area, wherein the buffer member has a smaller elastic modulus than the case and the sealing member, and wherein the low expansion member has a smaller linear expansion coefficient than the case and the sealing member.

An embodiment related to a stacked package is disclosed. The stacked package includes a conductive gang with gang legs electrically coupling a second component stacked over a first die to a package substrate. The first die is mounted over a die attach region of the package substrate and electrically coupled to the package substrate.

An embodiment related to a stacked package is disclosed. The stacked package includes a conductive gang with gang legs electrically coupling a second component stacked over a first die to a package substrate. The first die is mounted over a die attach region of the package substrate and electrically coupled to the package substrate.

A packaged semiconductor device and a method and apparatus for forming the same are disclosed. In an embodiment, a method includes bonding a device die to a first surface of a substrate; depositing an adhesive on the first surface of the substrate; depositing a thermal interface material on a surface of the device die opposite the substrate; placing a lid over the device die and the substrate, the lid contacting the adhesive and the thermal interface material; applying a clamping force to the lid and the substrate; and while applying the clamping force, curing the adhesive and the thermal interface material.

A packaged semiconductor device and a method and apparatus for forming the same are disclosed. In an embodiment, a method includes bonding a device die to a first surface of a substrate; depositing an adhesive on the first surface of the substrate; depositing a thermal interface material on a surface of the device die opposite the substrate; placing a lid over the device die and the substrate, the lid contacting the adhesive and the thermal interface material; applying a clamping force to the lid and the substrate; and while applying the clamping force, curing the adhesive and the thermal interface material.

There is provided a bonding paste capable of forming a uniform bonding layer by reducing occurrence of voids at edges even when a bonding area is large, and bonding method using the paste, and provides a metal paste for bonding containing at least metal nanoparticles (A) having a number average primary particle size of 10 to 100 nm, wherein a cumulative weight loss value (L.sub.100) when a temperature is raised from 40° C. to 100° C. is 75 or less, and a cumulative weight loss value (L.sub.150) when a temperature is raised from 40° C. to 150° C. is 90 or more, and a cumulative weight loss value (L.sub.200) when a temperature is raised from 40° C. to 200° C. is 98 or more, based on 100 cumulative weight loss value (L.sub.700) when the paste is heated from 40° C. to 700° C. at a heating rate of 3° C./min in a nitrogen atmosphere.

There is provided a bonding paste capable of forming a uniform bonding layer by reducing occurrence of voids at edges even when a bonding area is large, and bonding method using the paste, and provides a metal paste for bonding containing at least metal nanoparticles (A) having a number average primary particle size of 10 to 100 nm, wherein a cumulative weight loss value (L.sub.100) when a temperature is raised from 40° C. to 100° C. is 75 or less, and a cumulative weight loss value (L.sub.150) when a temperature is raised from 40° C. to 150° C. is 90 or more, and a cumulative weight loss value (L.sub.200) when a temperature is raised from 40° C. to 200° C. is 98 or more, based on 100 cumulative weight loss value (L.sub.700) when the paste is heated from 40° C. to 700° C. at a heating rate of 3° C./min in a nitrogen atmosphere.

Disclosed are exemplary embodiments of compressible foamed thermal interface materials. Also disclosed are methods of making and using compressible foamed thermal interface materials.

Disclosed are exemplary embodiments of compressible foamed thermal interface materials. Also disclosed are methods of making and using compressible foamed thermal interface materials.