An object of the present invention is to provide an electrically conductive paste and a sintered body thereof having a low electric resistance value and excellent electrical conductivity when made into a sintered body. An electrically conductive paste comprising: a flake-like silver powder having a median diameter D50 of 15 μm or less; a silver powder having a median diameter D50 of 25 μm or more; and a solvent, wherein the content of the flake-like silver powder is 15 to 70 parts by mass and the content of the silver powder having a median diameter D50 of 25 μm or more is 30 to 85 parts by mass based on 100 parts by mass in total of the flake-like silver powder and the silver powder having a median diameter D50 of 25 μm or more.

This paste composition includes silver particles (A), a thermosetting resin (B), a curing agent (C), and a solvent (D). A shrinkage rate after curing of the paste composition is 15% or less.

A dual-side cooling (DSC) semiconductor package includes a first metal-insulator-metal (MIM) substrate having a first insulator layer, first metallic layer, and second metallic layer. A second MIM substrate includes a second insulator layer, third metallic layer, and fourth metallic layer. The third metallic layer includes a first portion having a first contact area and a second portion, electrically isolated from the first portion, having a second contact area. A semiconductor die is coupled with the second metallic layer and is directly coupled with the third metallic layer through one or more solders, sintered layers, electrically conductive tapes, solderable top metal (STM) layers, and/or under bump metal (UBM) layers. The first contact area is electrically coupled with a first electrical contact of the die and the second contact area is electrically coupled with a second electrical contact of the die. The first and fourth metallic layers are exposed through an encapsulant.

A dual-side cooling (DSC) semiconductor package includes a first metal-insulator-metal (MIM) substrate having a first insulator layer, first metallic layer, and second metallic layer. A second MIM substrate includes a second insulator layer, third metallic layer, and fourth metallic layer. The third metallic layer includes a first portion having a first contact area and a second portion, electrically isolated from the first portion, having a second contact area. A semiconductor die is coupled with the second metallic layer and is directly coupled with the third metallic layer through one or more solders, sintered layers, electrically conductive tapes, solderable top metal (STM) layers, and/or under bump metal (UBM) layers. The first contact area is electrically coupled with a first electrical contact of the die and the second contact area is electrically coupled with a second electrical contact of the die. The first and fourth metallic layers are exposed through an encapsulant.

Provided is a semiconductor device including electronic components electrically joined to each other via a metal nanoparticle sintered layer, wherein the metal nanoparticle sintered layer has formed therein a metal diffusion region in which a metal constituting a metallization layer formed on a surface of one of the electronic components is diffused, and in which the metal is present in an amount of 10 mass % or more and less than 100 mass % according to TEM-EDS analysis, and wherein the metal diffusion region has a thickness smaller than a thickness of the metallization layer.

Provided is a semiconductor device including electronic components electrically joined to each other via a metal nanoparticle sintered layer, wherein the metal nanoparticle sintered layer has formed therein a metal diffusion region in which a metal constituting a metallization layer formed on a surface of one of the electronic components is diffused, and in which the metal is present in an amount of 10 mass % or more and less than 100 mass % according to TEM-EDS analysis, and wherein the metal diffusion region has a thickness smaller than a thickness of the metallization layer.

A method of forming a semiconductor package is provided. The method includes forming a metallization stack over a semiconductor die. Polymer particles are mounted over the metallization stack. Each of the polymer particles is coated with a first bonding layer. A heat spreader lid is bonded with the semiconductor die by reflowing the first bonding layer. A composite thermal interface material (TIM) structure is formed between the heat spreader lid and the semiconductor die during the bonding. The composite TIM structure includes the first bonding layer and the polymer particles embedded in the first bonding layer.

A method of forming a semiconductor package is provided. The method includes forming a metallization stack over a semiconductor die. Polymer particles are mounted over the metallization stack. Each of the polymer particles is coated with a first bonding layer. A heat spreader lid is bonded with the semiconductor die by reflowing the first bonding layer. A composite thermal interface material (TIM) structure is formed between the heat spreader lid and the semiconductor die during the bonding. The composite TIM structure includes the first bonding layer and the polymer particles embedded in the first bonding layer.

This film-shaped firing material is a film-shaped firing material containing sinterable metal particles and a binder component, in which, when the average thickness of the portion of the film-shaped firing material excluding the edge portion is deemed 100%, the average thickness of the edge portion of the film-shaped firing material is at least 5% thicker than the average thickness of the portion of the film-shaped firing material excluding the edge portion.

An electronic system is disclosed. In one example, the electronic system comprises an at least partially electrically conductive carrier, an electronic component, and an intermetallic connection structure connecting the carrier and the component. The intermetallic connection structure comprising an intermetallic mesh structure in a central portion of the intermetallic connection structure, and opposing exterior structures without intermetallic mesh and each arranged between the intermetallic mesh structure and the carrier or the component.