A mounting structure is used, which includes: a semiconductor element including an element electrode; a metal member; and a sintered body configured to bond the semiconductor element and the metal member is used, in which the sintered body contains a first metal and a second metal solid-dissolved in the first metal, the second metal is a metal having a diffusion coefficient in the first metal larger than a self-diffusion coefficient of the first metal, and a content ratio of the second metal relative to a total mass of the first metal and the second metal in the sintered body is equal to or lower than a solid solution limit of the second metal to the first metal.

A mounting structure is used, which includes: a semiconductor element including an element electrode; a metal member; and a sintered body configured to bond the semiconductor element and the metal member is used, in which the sintered body contains a first metal and a second metal solid-dissolved in the first metal, the second metal is a metal having a diffusion coefficient in the first metal larger than a self-diffusion coefficient of the first metal, and a content ratio of the second metal relative to a total mass of the first metal and the second metal in the sintered body is equal to or lower than a solid solution limit of the second metal to the first metal.

Various embodiments may provide a semiconductor package. The semiconductor package may include a first electrical component, a second electrical component, a first heat sink, and a second heat sink bonded to a first package interconnection component and a second package interconnection component. The first package interconnection component and the second package interconnection component may provide lateral and vertical interconnections in the package.

There is provided a bonding material which forms a bonding portion between two objects, which material contains (1) first metal particles comprising a first metal and having a median particle diameter in the range of 20 nm to 1 μm, and (2) second metal particles comprising, as a second metal, at least one alloy of Sn and at least one selected from Bi, In and Zn and having a melting point of not higher than 200° C.

A copper paste for joining contains metal particles and a dispersion medium, in which the copper paste for joining contains copper particles as the metal particles, and the copper paste for joining contains dihydroterpineol as the dispersion medium. A method for manufacturing a joined body is a method for manufacturing a joined body which includes a first member, a second member, and a joining portion that joins the first member and the second member, the method including: a first step of printing the above-described copper paste for joining to at least one joining surface of the first member and the second member to prepare a laminate having a laminate structure in which the first member, the copper paste for joining, and the second member are laminated in this order; and a second step of sintering the copper paste for joining of the laminate.

A semiconductor device has a resistance element including a metal block, a resin layer disposed on the metal block, and a resistance film disposed on the resin layer and an insulated circuit board including an insulating plate and a circuit pattern disposed on the insulating plate and having a bonding area on a front surface thereof to which a back surface of the metal block of the resistance element is bonded. The area of the circuit pattern is larger in plan view than that of a front surface of the resistance element. The metal block has a thickness greater than that of the circuit pattern in a direction orthogonal to the back surface of the metal block. As a result, the metal block properly conducts heat generated by the resistance film of the resistance element to the circuit pattern.

A semiconductor device has a resistance element including a metal block, a resin layer disposed on the metal block, and a resistance film disposed on the resin layer and an insulated circuit board including an insulating plate and a circuit pattern disposed on the insulating plate and having a bonding area on a front surface thereof to which a back surface of the metal block of the resistance element is bonded. The area of the circuit pattern is larger in plan view than that of a front surface of the resistance element. The metal block has a thickness greater than that of the circuit pattern in a direction orthogonal to the back surface of the metal block. As a result, the metal block properly conducts heat generated by the resistance film of the resistance element to the circuit pattern.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

The present disclosure is directed to a hybrid conductive ink including: silver nanoparticles and eutectic low melting point alloy particles, wherein a weight ratio of the eutectic low melting point alloy particles and the silver nanoparticles ranges from 1:20 to 1:5. Also provided herein are methods of forming an interconnect including a) depositing a hybrid conductive ink on a conductive element positioned on a substrate, wherein the hybrid conductive ink comprises silver nanoparticles and eutectic low melting point alloy particles, the eutectic low melting point alloy particles and the silver nanoparticles being in a weight ratio from about 1:20 to about 1:5; b) placing an electronic component onto the hybrid conductive ink; c) heating the substrate, conductive element, hybrid conductive ink and electronic component to a temperature sufficient i) to anneal the silver nanoparticles in the hybrid conductive ink and ii) to melt the low melting point eutectic alloy particles, wherein the melted low melting point eutectic alloy flows to occupy spaces between the annealed silver nanoparticles, d) allowing the melted low melting point eutectic alloy of the hybrid conductive ink to harden and fuse to the electronic component and the conductive element, thereby forming an interconnect. Electrical circuits including conductive traces and, optionally, interconnects formed with the hybrid conductive ink are also provided.