The present invention relates to a conductive composition containing a conductive metal powder and a resin component, in which the conductive metal powder contains at least a metal flake having a crystalline structure in which a metal crystal grows in a flake shape, and the resin component contains an aromatic amine skeleton.

The present invention relates to a conductive composition containing a conductive metal powder and a resin component, in which the conductive metal powder contains at least a metal flake having a crystalline structure in which a metal crystal grows in a flake shape, and the resin component contains an aromatic amine skeleton.

A conductive composition, which can form bonded portions and is capable of maintaining a thickness of the bonded portions and bonding strength, and which includes: (A) silver fine particles having a number average particle diameter of primary particles of 40 nm to 400 nm, (B) a solvent, and (C) thermoplastic resin particles having a maximal value of an endothermic peak in a DSC chart, determined by a measurement using a differential scanning calorimeter, within a range of 80° C. to 170° C.

A conductive composition, which can form bonded portions and is capable of maintaining a thickness of the bonded portions and bonding strength, and which includes: (A) silver fine particles having a number average particle diameter of primary particles of 40 nm to 400 nm, (B) a solvent, and (C) thermoplastic resin particles having a maximal value of an endothermic peak in a DSC chart, determined by a measurement using a differential scanning calorimeter, within a range of 80° C. to 170° C.

An anisotropic conductive film with a structure wherein an electrically insulting adhesive base layer and cover layer are stacked, and electrically conductive particles are disposed at lattice points with a planar lattice pattern in the vicinity of the interface of the layers. In the anisotropic conductive film, a proportion of lattice points at which no electrically conductive particles are disposed with respect to all lattice points with the planar lattice pattern assumed in any reference region is 25% or less, and some of the electrically conductive particles disposed at lattice points with planar lattice pattern are disposed to be shifted in longitudinal direction of anisotropic conductive film with respect to corresponding lattice points, and a shift amount defined as a distance between a plane projection center of the electrically conductive particles disposed to be shifted and the corresponding lattice point is less than 50% the electrically conductive particles' average diameter.

A manufacturing method includes the step of laminating a sheet assembly onto chips arranged on a processing tape, where the sheet assembly has a multilayer structure including a base and a sinter-bonding sheet and is laminated so that the sinter-bonding sheet faces the chips, and subsequently removing the base B from the sinter-bonding sheet. The chips on the processing tape are picked up each with a portion of the sinter-bonding sheet adhering to the chip, to give sinter-bonding material layer-associated chips. The sinter-bonding material layer-associated chips are temporarily secured through the sinter-bonding material layer to a substrate. The sinter-bonding material layers lying between the temporarily secured chips and the substrate are converted through a heating process into sintered layers, to bond the chips to the substrate. The semiconductor device manufacturing method is suitable for efficiently supplying a sinter-bonding material to semiconductor chips while reducing loses of the sinter-bonding material.

A manufacturing method includes the step of laminating a sheet assembly onto chips arranged on a processing tape, where the sheet assembly has a multilayer structure including a base and a sinter-bonding sheet and is laminated so that the sinter-bonding sheet faces the chips, and subsequently removing the base B from the sinter-bonding sheet. The chips on the processing tape are picked up each with a portion of the sinter-bonding sheet adhering to the chip, to give sinter-bonding material layer-associated chips. The sinter-bonding material layer-associated chips are temporarily secured through the sinter-bonding material layer to a substrate. The sinter-bonding material layers lying between the temporarily secured chips and the substrate are converted through a heating process into sintered layers, to bond the chips to the substrate. The semiconductor device manufacturing method is suitable for efficiently supplying a sinter-bonding material to semiconductor chips while reducing loses of the sinter-bonding material.

A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach material between the semiconductor die and the substrate. A conformal structure which includes a pressure transmissive material contacts at least a portion of a top surface of the semiconductor die. A pressure is applied to the conformal structure and in turn, the pressure is transmitted to the top surface of the semiconductor die by the pressure transmissive material. While the pressure is applied, concurrently encapsulating the assembly with a molding compound and exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter.

In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor chip having a first side and an opposite second side, and a chip contact pad disposed on the first side of the semiconductor chip. A dielectric liner is disposed over the semiconductor chip. The dielectric liner includes a plurality of openings over the chip contact pad. A interconnect contacts the semiconductor chip through the plurality of openings at the chip contact pad.

In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor chip having a first side and an opposite second side, and a chip contact pad disposed on the first side of the semiconductor chip. A dielectric liner is disposed over the semiconductor chip. The dielectric liner includes a plurality of openings over the chip contact pad. A interconnect contacts the semiconductor chip through the plurality of openings at the chip contact pad.