A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

A manufacturing method includes the step of laminating a sheet assembly onto chips arranged on a processing tape, where the sheet assembly has a multilayer structure including a base and a sinter-bonding sheet and is laminated so that the sinter-bonding sheet faces the chips, and subsequently removing the base B from the sinter-bonding sheet. The chips on the processing tape are picked up each with a portion of the sinter-bonding sheet adhering to the chip, to give sinter-bonding material layer-associated chips. The sinter-bonding material layer-associated chips are temporarily secured through the sinter-bonding material layer to a substrate. The sinter-bonding material layers lying between the temporarily secured chips and the substrate are converted through a heating process into sintered layers, to bond the chips to the substrate. The semiconductor device manufacturing method is suitable for efficiently supplying a sinter-bonding material to semiconductor chips while reducing loses of the sinter-bonding material.

A manufacturing method includes the step of laminating a sheet assembly onto chips arranged on a processing tape, where the sheet assembly has a multilayer structure including a base and a sinter-bonding sheet and is laminated so that the sinter-bonding sheet faces the chips, and subsequently removing the base B from the sinter-bonding sheet. The chips on the processing tape are picked up each with a portion of the sinter-bonding sheet adhering to the chip, to give sinter-bonding material layer-associated chips. The sinter-bonding material layer-associated chips are temporarily secured through the sinter-bonding material layer to a substrate. The sinter-bonding material layers lying between the temporarily secured chips and the substrate are converted through a heating process into sintered layers, to bond the chips to the substrate. The semiconductor device manufacturing method is suitable for efficiently supplying a sinter-bonding material to semiconductor chips while reducing loses of the sinter-bonding material.

An anisotropic conductive film (ACF), a bonding structure, and a display panel, and their fabrication methods are provided. The ACF includes a resin gel and a plurality of conductive particles dispersed in the resin gel. The plurality of conductive particles is aligned and connected, in response to an electric field, to form a conduction path in the resin gel. The bonding structure includes the anisotropic conductive film (ACF) sandwiched between first and second substrates. The display panel includes the bonding structure.

An anisotropic conductive film (ACF), a bonding structure, and a display panel, and their fabrication methods are provided. The ACF includes a resin gel and a plurality of conductive particles dispersed in the resin gel. The plurality of conductive particles is aligned and connected, in response to an electric field, to form a conduction path in the resin gel. The bonding structure includes the anisotropic conductive film (ACF) sandwiched between first and second substrates. The display panel includes the bonding structure.

The present invention provides a method for producing a semiconductor device, including: a semiconductor chip-mounting step of subsequently pressing a plurality of semiconductor chips by a first pressing member to respectively bond the plurality of semiconductor chips to a plurality of mounting areas provided on a substrate, wherein the bonding is performed in a state where adhesive sheets are respectively interposed between the plurality of semiconductor chips and the plurality of mounting areas, each of the adhesive sheets includes sinterable metal particles that can be sintered by heating at a temperature of 400° C. or less, and the first pressing member is heated to a temperature, at which the sinterable metal particles can be sintered.

A thermosetting sheet according to the present invention includes: a thermosetting resin; a thermoplastic resin; and conductive particles. The conductive particles includes silver particles having an average particle size D.sub.50 of 0.01 μm or more and 10 μm or less, and having a circularity in cross section of 0.7 or more. The thermosetting sheet has a viscosity at 100° C. of 20 kPa.Math.s or more and 3000 kPa.Math.s or less.

A thermosetting sheet according to the present invention includes: a thermosetting resin; a thermoplastic resin; and conductive particles. The conductive particles includes silver particles having an average particle size D.sub.50 of 0.01 μm or more and 10 μm or less, and having a circularity in cross section of 0.7 or more. The thermosetting sheet has a viscosity at 100° C. of 20 kPa.Math.s or more and 3000 kPa.Math.s or less.

A first anisotropic conductive film 1A or a second anisotropic conductive film 1B has a first insulating resin layer 2 and a second insulating resin layer 3. The first insulating resin layer 2 is formed of a photopolymerized resin, and the second insulating resin layer 3 is formed of a polymerizable resin. Conductive particles 10 are disposed in a single layer on a surface of the first insulating resin layer 2 on a side of the second insulating resin layer 3. The first anisotropic conductive film further has a third insulating resin layer 4 formed of a polymerizable resin, and the second anisotropic conductive film 1B has an intermediate insulating resin layer 6. The intermediate insulating resin layer 6 is formed of a resin containing no polymerization initiator, and is in contact with the conductive particles 10. These anisotropic conductive films have favorable connection reliability.

A first anisotropic conductive film 1A or a second anisotropic conductive film 1B has a first insulating resin layer 2 and a second insulating resin layer 3. The first insulating resin layer 2 is formed of a photopolymerized resin, and the second insulating resin layer 3 is formed of a polymerizable resin. Conductive particles 10 are disposed in a single layer on a surface of the first insulating resin layer 2 on a side of the second insulating resin layer 3. The first anisotropic conductive film further has a third insulating resin layer 4 formed of a polymerizable resin, and the second anisotropic conductive film 1B has an intermediate insulating resin layer 6. The intermediate insulating resin layer 6 is formed of a resin containing no polymerization initiator, and is in contact with the conductive particles 10. These anisotropic conductive films have favorable connection reliability.