A liquid cooled coldplate has a tub with an inlet port and an outlet port and a plurality of pockets recessed within a top surface of the tub. Each pocket has a peripheral opening and a ledge, the ledge disposed inwardly and downwardly from the peripheral opening. The inlet port and outlet port are in fluid communication with the pocket via an inlet slot and an outlet slot. A plurality of cooling plates are each received by a pocket and recessed within the pocket. Each cooling plate comprises an electronics side for receiving electronics and enhanced side for cooling the cooling plate. The enhanced side of the cooling plate comprises a plurality of pins formed by micro deformation technology. The tub may be formed by extrusion.

A wiring substrate includes a first wiring structure and a second wiring structure stacked thereon. The first wiring structure includes a first insulation layer and a via wiring extending through the first insulation layer. The second wiring structure includes a first wiring layer formed on the first insulation layer and the via wiring, and a first plane layer stacked on the first insulation layer and at least partially grid-shaped in a plan view to define second through holes. A second insulation layer is stacked on the first insulation layer to fill the second through holes and cover the first plane layer and the first wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The second through holes each include a lower open end and an upper open end having a smaller open width than the lower open end.

A printed wiring board is provided with a wiring layer, a first ground layer, a second ground layer, a grounding through-hole, a signal through-hole, a first clearance, and a second clearance. The wiring layer has a signal line. The first ground layer has a first ground plane. The second ground layer is positioned between the wiring layer and the first ground layer and has a second ground plane. The grounding through-hole passes through the wiring layer, the first ground layer, and the second ground layer and is connected to the second ground plane. The signal through-hole passes through the wiring layer, the first ground layer, and the second ground layer and is connected to the signal line. The first clearance is formed in the first ground layer, is positioned in the vicinity of the signal through-hole and the grounding through-hole, and separates the first ground plane from the signal through-hole and the grounding through-hole. The second clearance is formed in the second ground layer, is positioned in the vicinity of the signal through-hole, and separates the second ground plane from the signal through-hole.

A circuit structure is provided, which includes a plurality of conductive posts, and a plurality of first and second conductive pads formed on two opposite end surfaces of the conductive posts, respectively. A length of each of the first conductive pads is greater than a width of the first conductive pad so as to reduce an occupation area of the first conductive pad along the width and increase a distance between adjacent first conductive pads, thereby increasing the wiring density and meeting the wiring demand.

A via in a printed circuit board is composed of a patterned metal layer that extends through a hole in dielectric laminate material. A layer of catalytic adhesive coats walls within the hole. The patterned metal layer is placed over the catalytic adhesive within the hole.

A circuit structure is provided, which includes a plurality of conductive posts, and a plurality of first and second conductive pads formed on two opposite end surfaces of the conductive posts, respectively. A length of each of the first conductive pads is greater than a width of the first conductive pad so as to reduce an occupation area of the first conductive pad along the width and increase a distance between adjacent first conductive pads, thereby increasing the wiring density and meeting the wiring demand.

A via in a printed circuit board is composed of a patterned metal layer that extends through a hole in dielectric laminate material that has been covered with catalytic adhesive material on both faces of the dielectric laminate material. The layer of catalytic adhesive coats a portion of the dielectric laminate material around the hole. The patterned metal layer is placed over the catalytic adhesive material on both faces of the dielectric laminate material and within the hole.

One embodiment of the invention comprises an improved method for making a via structure for use in a printed circuit board (PCB). The via allows for the passage of a signal from one signal plane to another in the PCB, and in so doing transgresses the power and ground planes between the signal plane. To minimize EM disturbance between the power and ground planes, signal loss due to signal return current, and via-to-via coupling, the via is shielded within two concentric cylinders, each coupled to one of the power and ground planes.

A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.