A stacked semiconductor device structure includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a recessed surface portion bounded by opposing sidewall portions extending outward to define a recessed region. A conductive layer is disposed along at least the recessed surface portion. The second semiconductor device is disposed within the recessed region and is electrically connected to the conductive layer. In one embodiment, the stacked semiconductor device is connected to a conductive lead frame and is at least partially encapsulated by a package body.

A solid-state imaging device includes a pixel having a photoelectric conversion element which generates a charge in response to incident light, a first transfer gate which transfers the charge from the photoelectric conversion element to a charge holding section, and a second transfer gate which transfers the charge from the charge holding section to a floating diffusion. The first transfer gate includes a trench gate structure having at least two trench gate sections embedded in a depth direction of a semiconductor substrate, and the charge holding section includes a semiconductor region positioned between adjacent trench gate sections.

Embodiments related to the manufacturing of an imager device and an imager device are disclosed. Embodiments associated with methods of an imager device are also disclosed.

System, devices and methods are presented that provide an imaging array fabrication process method, comprising fabricating an array of semiconductor imaging elements, interconnecting the elements with stretchable interconnections, and transfer printing the array with a pre-strained elastomeric stamp to a secondary non-planar surface.

A MCP photodetector assembly includes an anode plate including a plurality of electrical traces positioned thereon, a plurality of MCPs and a plurality of grid spacers. The MCPs are positioned between the grid spacers. The grid spacers have a grid spacer shape defining at least one aperture. A plurality of shims are positioned between the grid spacers and the MCPs so as to form a stack positioned on the anode plate. Each of the plurality of shims have a shim shape which is the same as the grid spacer shape such that each of the plurality of shims and each of the plurality of grid spacers overlap so as to define at least one MCP aperture. At least a portion of the plurality of MCPs are positioned within the MCP aperture. The shims are structured to electrically couple the MCPs to the anode plate.

Fabricating an optics wafer includes providing a wafer comprising a core region composed of a glass-reinforced epoxy, the wafer further comprising a first resin layer on a top surface of the core region and a second resin layer on a bottom surface of the core region. The core region and first and second resin layers are substantially non-transparent for a specific range of the electromagnetic spectrum. The wafer further includes vertical transparent regions that extend through the core region and the first and second resin layers and are composed of a material that is substantially transparent for the specific range of the electromagnetic spectrum. The wafer is thinned, for example by polishing, from its top surface and its bottom surface so that a resulting thickness is within a predetermined range without causing glass fibers of the core region to become exposed. Respective optical structures are provided on one or more exposed surfaces of at least some of the transparent regions.

A time-of-flight detection pixel includes a photosensitive area including a first doped layer and a charge collection area extending in the first doped layer. At least two charge storage areas extend from the charge collection area, each including a first well more heavily doped than the charge collection area and separated from the charge collection area by a first portion of the first doped layer which is coated with a gate. Each charge storage area is laterally delimited by two insulated conductive electrodes, extending parallel to each other and facing each other. A second heavily doped layer of opposite conductivity coats the pixel except for at each portion of the first doped layer coated with the gate.

A pixel is formed on a semiconductor substrate that includes a photosensitive area having a first doped layer and a charge collection area of a first conductivity type extending through at least part of the first doped layer. At least two charge storage areas, each including a well of the first conductivity type, are separated from the charge collection area at least by a first portion of the first layer. The first portion is covered by a first gate. Each charge storage area is laterally delimited by two insulated conductive electrodes. A second doped layer of the second conductivity type covers the charge collection area and the charge storage areas.

Various techniques, methods, devices and apparatus are provided where an isolation layer is provided at a peripheral region of the substrate, and one or more metal layers are deposited onto the substrate.

Embodiments described herein relate to a dual-band photodetector. The dual-band photodetector includes a barrier layer (10) disposed between two infrared absorption layers (8, 12) wherein the barrier layer (10) is lattice matched to at least one of the infrared absorption layers (8, 12). Furthermore, one infrared absorption layer includes dilute nitride to adjust the band gap to a desired cut-off wavelength while maintaining valence-band alignment with the barrier layer. Embodiments also relate to a system and processes for producing the photodetector fabricated from semiconductor materials.