In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.

A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.

A process of forming a gate insulating film in a silicon carbide semiconductor device. The process includes performing a first stage of a nitriding heat treatment by a gas containing oxygen and nitrogen, followed by depositing an oxide film, and then performing a second stage of the nitriding heat treatment by a gas containing nitric oxide and nitrogen. The amount of nitrogen at the treatment starting point of the first stage of the nitriding heat treatment is greater than the amount of nitrogen at the treatment starting point of the second stage of the nitriding heat treatment. The amount of nitrogen at the treatment ending point of the second stage of the nitriding heat treatment is greater than the amount of nitrogen at the treatment ending point of the first stage of the nitriding heat treatment.

To reduce on-resistance while suppressing a characteristic variation increase of a vertical MOSFET with a Super Junction structure, the vertical MOSFET includes a semiconductor substrate having an n-type drift region, a p-type base region formed on the surface of the n-type drift region, a plurality of p-type column regions disposed in the n-type drift region at a lower portion of the p-type base region by a predetermined interval, a plurality of trenches whose bottom surface reaches a position deeper than the p-type base region and that is disposed between the adjacent p-type column regions, a plurality of gate electrodes formed in the plurality of trenches, and an n-type source region formed on the side of the gate electrode in the p-type base region.

A field plate electrode FP is formed inside the trench TR via an insulating film IF1. The insulating film IF1 is retracted so that the position of the upper surface of the insulating film IF1 is lower than the position of the upper surface of the field plate electrode FP. An embedded insulating film EF1 is formed to cover the field plate electrode FP and the insulating film IF1. The embedded insulating film EF1 is retracted so that the position of the upper surface of the embedded insulating film EF1 is lower than the position of the upper surface of the field plate electrode FP. A gate insulating film GI is formed inside the trench TR, and an insulating film IF2 is formed to cover the field plate electrode FP. A gate electrode is formed on the field plate electrode FP via the insulating film IF2.

Semiconductor device has a cell region and a peripheral region, and has a drift layer, a trench, an gate dielectric film on an inner wall of the trench, a gate electrode, and a p-type first semiconductor region below the trench in the cell region on a semiconductor substrate. Further, in the peripheral region on the semiconductor substrate, p-type second semiconductor region is formed in the same layer as the p-type first semiconductor region, a width of the p-type first semiconductor region and a width of the p-type second semiconductor region are different.

A semiconductor device includes a semiconductor layer; a trench formed in the semiconductor layer and including a side wall, an insulation layer formed on the semiconductor layer; and a gate electrode arranged in the trench. The insulation layer includes a gate insulation portion located between the semiconductor layer and the gate electrode, and covering the side wall of the trench. The gate electrode includes a first conductive portion contacting the gate insulation portion, and a second conductive portion including a side surface contacting the first conductive portion. The first conductive portion is formed from polysilicon, and the second conductive portion is formed from metal.

A semiconductor device includes a chip that has a main surface, a gate resistor that includes a trench resistor structure formed in the main surface, a gate pad that has a lower resistance value than the trench resistor structure and is arranged on the main surface such as to be electrically connected to the trench resistor structure, and a gate wiring that has a lower resistance value than the trench resistor structure and is arranged on the main surface such as to be electrically connected to the gate pad via the trench resistor structure.

A semiconductor device includes a chip having a first main surface which serves as a device surface and a second main surface which serves as a non-device surface, and a first conductivity type drift gradient region formed in the chip, and having a concentration profile in which an impurity concentration of an end portion on the first main surface side is lower than an impurity concentration of an end portion on the second main surface side.

A semiconductor device includes a semiconductor layer including a first surface and a second surface opposite to the first surface; a source trench formed in the semiconductor layer and including a side wall that is continuous with the second surface; an insulation layer formed on the second surface of the semiconductor layer; an embedded electrode arranged in the source trench and insulated from the side wall of the source trench by the insulation layer; a source interconnection formed on the insulation layer; and a source contact plug electrically connecting the source interconnection to the semiconductor layer. The source contact plug contacts the embedded electrode, and the source contact plug contacts the semiconductor layer via a part of the side wall of the source trench.