The present disclosure describes a method that includes forming a first two-dimensional (2D) layer on a first substrate and attaching a second 2D layer to a carrier film. The method also includes bonding the second 2D layer to the first 2D layer to form a heterostack including the first and second 2D layers. The method further includes separating the first 2D layer of the heterostack from the first substrate and attaching the heterostack to a second substrate. The method further includes removing the carrier film from the second 2D layer.

A semiconductor device includes a substrate, a channel layer, an insulating layer, source/drain contacts, a gate dielectric layer, and a gate electrode. The channel layer over the substrate and includes two dimensional (2D) material. The insulating layer is on the channel layer. The source/drain contacts are over the channel layer. The gate dielectric layer is over the insulating layer and the channel layer. The gate electrode is over the gate dielectric layer and between the source/drain contacts.

A semiconductor device includes a channel on a substrate. The channel includes a 2-dimensional material. A gate insulating layer is on a first portion of the channel. A gate electrode is on a portion of the gate insulating layer. First and second contact patterns are on second portions of the channel, respectively. Each of the first and second contact patterns includes a 2-dimensional material having an intercalation material disposed therein. First and second source/drain electrodes are on the first and second contact patterns, respectively. Each of the first and second source/drain electrodes includes a metal.

Embodiments provide a transistor structure, a semiconductor structure and a fabrication method thereof. The method for fabricating a transistor structure includes: providing a substrate; forming a channel layer on an upper surface of the substrate, the channel layer including a two-dimensional layered transition metal material layer; forming a source and a drain on two opposite sides of the channel layer, respectively; forming a gate dielectric layer on the upper surface of the substrate, the gate dielectric layer covering the channel layer, the source, and the drain; and forming a gate on an upper surface of the gate dielectric layer, the gate being positioned at least directly above the channel layer.

The present application provides a logic gate device. The logic gate device includes a gate electrode, a gate insulating layer, a bottom electrode, a two-dimensional semiconductor layer, a first top electrode and a second electrode. The gate insulating layer is located on the gate electrode. The bottom electrode is located on the gate insulating layer. The two-dimensional semiconductor layer is located on the bottom electrode and simultaneously covers the gate insulating layer. The first top electrode and the second electrode are located on the two-dimensional semiconductor layer. The bottom electrode, the two-dimensional semiconductor layer and the gate insulating layer form an air gap, and the air gap is distributed at both sides of the bottom electrode. The gate electrode is configured to connect a gate voltage, and the first top electrode and the second top electrode are configured to connect a signal input terminal.

Disclosed are a negative transconductance device and a multi-valued memory device using the same. The negative transconductance includes a monolithic WSe.sub.2 semiconductor thin film; a first doped layer disposed on a first area of the WSe.sub.2 semiconductor thin film; a second doped layer disposed on a second area of the WSe.sub.2 semiconductor thin film so as to supply holes to the second area, wherein the second area is spaced apart from the first area; a first electrode electrically connected to the first area of the WSe.sub.2 semiconductor thin film; a second electrode electrically connected to the second area of the WSe.sub.2 semiconductor thin film; and a third electrode for applying a gate voltage to the first area and the second area of the WSe.sub.2 semiconductor thin film, and to a third area thereof located between the first and second areas.

According to embodiments of the present disclosure, two-dimensional (2D) materials may be used as nanosheet channels for multi-channel transistors. Nanosheet channels made two-dimensional (2D) materials can achieve the same drive current at smaller dimensions and/or fewer number of channels, therefore enable scaling down and/or boost derive current. Embodiments of the present disclosure also provide a solution of P-type and N-type balancing in a device without increasing footprint of the device.

A semiconductor device includes channel structures spaced apart in a vertical direction; lower/upper first gate insulation patterns contacting lower/upper surfaces of the channel structures; a gate electrode surrounding lower/upper surfaces and a sidewall of the channel structures; and source/drain layers at sides of the gate electrode, wherein the channel structures include first/second 2D material layers stacked in the vertical direction, the first 2D material layer includes a semiconducting TMD including a first transition metal and first chalcogen elements that are bonded at lower/upper sides of the first transition metal, the second 2D material layer includes a second transition metal and a second chalcogen element, the second chalcogen element being bonded at a lower side of the second transition metal, and the second transition metal included in the second 2D material layer is covalently or ionically bonded with an element of the upper first gate insulation pattern.

A method of fabricating a semiconductor device includes forming a semiconductor layer, the semiconductor layer including a two-dimensional semiconductor material, forming a sacrificial layer on the semiconductor layer, forming a metal contact layer on the sacrificial layer, and removing the sacrificial layer. After the sacrificial layer is removed, the semiconductor layer and the metal contact layer are bonded to each other through a van der Waals bond.

A semiconductor device includes a channel on a substrate. The channel includes a 2-dimensional material. A gate insulating layer is on a first portion of the channel. A gate electrode is on a portion of the gate insulating layer. First and second contact patterns are on second portions of the channel, respectively. Each of the first and second contact patterns includes a 2-dimensional material having an intercalation material disposed therein. First and second source/drain electrodes are on the first and second contact patterns, respectively. Each of the first and second source/drain electrodes includes a metal.