A semiconductor structure is provided that includes a silicon germanium alloy fin having a second germanium content located on a first portion of a substrate. The structure further includes a laterally graded silicon germanium alloy material portion located on a second portion of the substrate. The laterally graded silicon germanium alloy material portion is spaced apart from the silicon germanium alloy fin and has end portions having the second germanium content and a middle portion located between the end portions that has a first germanium content that is less than the second germanium content.

The present disclosure provides an FET structure including a transistor of a first conductive type. The transistor includes a substrate having a region of a second conductive type, a channel between source and drain, and a gate over the channel. The channel includes dopants of the first conductive type. The gate includes a work function setting layer of the second conductive type. The present disclosure also provides a method for manufacturing an FET with multi-threshold voltages scheme. The method includes exposing channels of a first transistor of a first conductive type and a first transistor of a second conductive type from a first mask, doping the channels with dopants of the first conductive type, exposing channels of a second transistor of the first conductive type and a second conductive type from a second mask, and doping the channels with dopants of the second conductive type.

A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.

The present invention provides a field effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first III-V compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first III-V compound layer, and source/drain electrodes are respectively located at each side of the gate electrode and on the first III-V compound layer. According to the present invention, the band width of the barrier layer is greater than that of the first III-V compound layer, and the band curvatures of the barrier layer and the first III-V compound layer are different, therefore, a two-dimensional electron gas (2DEG) is formed in the first III-V compound layer near the barrier layer boundary. Since the 2DEG has higher mobility, the performance of the filed effect transistor improved. Besides, the performance of the filed effect transistor also improved due to the structure is a gate-all-around structure.

A method for forming a fin device includes forming semiconductor fins over a first dielectric layer. A second dielectric layer is directionally deposited into or on the first dielectric layer and on tops of the fins on horizontal surfaces. The second dielectric layer is configured to protect the first dielectric layer in subsequent processing. Sidewalls of the fins are precleaned while the first dielectric layer is protected by the second dielectric layer. The second dielectric layer is removed to expose the first dielectric layer in a protected state.

A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is formed on the substrate layer extending away from the channel layer. A source-drain (SD) stressor structure is disposed on sidewalls of the channel layer over the oxide layer. A gate stack including a gate electrode layer and a gate dielectric layer covers a portion of the channel layer and extends in a second direction perpendicular to the first direction.

A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate including a first semiconductor material is provided. The semiconductor substrate includes a dielectric structure formed thereon, and the dielectric structure includes at least a recess formed therein. A first epitaxial layer is then formed in the recess. The first epitaxial layer includes at least a second semiconductor material that a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. Subsequently, a thermal oxidation process is performed to the first epitaxial layer thereby forming a semiconductor layer at a bottom of the recess and a silicon oxide layer on the semiconductor layer. After removing the silicon oxide layer, a second epitaxial layer is formed on the semiconductor layer in the recess.

After forming an epitaxial semiconductor layer on portions of a semiconductor located on opposite sides of a sacrificial gate structure, dopants from the epitaxial semiconductor layer are diffused into the semiconductor fin to form a dopant-containing semiconductor fin. A sacrificial gate stack is removed to provide a gate cavity that exposes a portion of the dopant-containing semiconductor fin. The exposed portion of the dopant-containing semiconductor fin is removed to provide an opening underneath the gate cavity. A channel which is undoped or less doped than remaining portions of the dopant-containing semiconductor fin is epitaxially grown at least from the sidewalls of the remaining portions of the dopant-containing semiconductor fin. Abrupt junctions are thus formed between the channel region and the remaining portions of the dopant-containing semiconductor fin.

A method of fabricating a semiconductor device is disclosed. The method includes the steps of forming recesses in a semiconductor substrate; epitaxial growing a first SiGe seed layer with constant Ge content in the recesses; epitaxial growing a second SiGe layer with a constant Ge content higher than the Ge content of first SiGe seed layer on the first SiGe seed layer; epitaxial growing a third SiGe layer with a constant Ge content lower than the Ge content of the second SiGe layer; and forming a cap layer on the third SiGe layer.

The disclosed subject matter provides a Fin-FET with a thinned-down InP layer and thinning-down method thereof. In a Fin-FET, the fin structure is made of InGaAs and an InP layer is formed to cover the fin structure. The InP layer is obtained from an initial InP layer formed on the fin structure through a thinning down process including converting a surface portion of the InP layer into a Phosphorus-rich layer and removing the Phosphorus-rich layer. The thickness of the ultimately-formed InP layer is less than or equal to 1 nm. According to the disclosed method, the InP layer in the Fin-FET may be easily thinned down, and during the thinning-down process, contamination may be avoided.