The present invention provides a method for manufacturing the N-type TFT, which includes subjecting a light shielding layer to a grating like patternization treatment for controlling different zones of a poly-silicon layer to induce difference of crystallization so as to have different zones of the poly-silicon layer forming crystalline grains having different sizes, whereby through just one operation of ion doping, different zones of the poly-silicon layer have differences in electrical resistivity due to difference of grain size generated under the condition of identical doping concentration to provide an effect equivalent to an LDD structure for providing the TFT with a relatively low leakage current and improved reliability. Further, since only one operation of ion injection is involved, the manufacturing time and manufacturing cost can be saved, damages of the poly-silicon layer can be reduced, the activation time can be shortened, thereby facilitating the manufacture of flexible display devices.

A method of manufacturing a substrate includes: irradiating, along a first path, a laser beam emitted from a source onto a substrate, wherein the substrate includes a target layer of the laser beam, and wherein the substrate is disposed on a stage; and irradiating, along a second path, a portion the laser beam, which was emitted from the source and reached the target layer, by reflecting the laser beam back onto the target layer using a reflection mirror. An area of a second region of the target layer is greater than an area of a first region of the target layer, wherein the laser beam is irradiated along the second path in the second region, and the laser beam is irradiated along the first path in the first region.

A method of manufacturing a thin film transistor is disclosed. In one aspect, the method includes forming an active layer over a substrate and forming a gate insulating layer containing a dopant over the active layer. The method also includes irradiating laser light onto the gate insulating layer such that the dopant of the gate insulating layer diffuses into the active layer.

Solved is a problem of attenuation of output amplitude due to a threshold value of a TFT when manufacturing a circuit with TFTs of a single polarity. In a capacitor (105), a charge equivalent to a threshold value of a TFT (104) is stored. When a signal is inputted thereto, the threshold value stored in the capacitor (105) is added to a potential of the input signal. The thus obtained potential is applied to a gate electrode of a TFT (101). Therefore, it is possible to obtain the output having a normal amplitude from an output terminal (Out) without causing the amplitude attenuation in the TFT (101).

The present invention provides a low temperature polysilicon thin film transistor and a fabricating method thereof. According to the method, a laser annealing process is performed to a remained portion of a a-Si layer on a substrate to form a first lightly doped drain (LDD) terminal, a second LDD terminal, a first phosphor material structure and a second phosphor material structure. A gate metal layer is then formed on the remained portion of the a-Si layer. A source metal layer and a drain metal layer are formed on the first doped layer and the second doped layer located at opposite sides of the gate metal layer, respectively. The present invention use the high temperature of the laser annealing process to perform a heat diffusion of phosphor material to form the LDD terminal and the phosphor material structure, the times of photomasks are used is reduced, and the process is simplified.

A method of manufacturing a polysilicon (poly-Si) layer, a method of manufacturing an organic light-emitting display apparatus using the method, and an organic light-emitting display apparatus manufactured by using the method. The method includes forming an amorphous silicon (a-Si) layer on a substrate having first and second areas, thermally treating the a-Si layer to partially crystallize the a-Si layer into a partially crystallized Si layer, removing a thermal oxide layer through a thermal treatment, selectively irradiating the first areas with laser beams to crystallize the partially crystallized Si layer.

A display may have an array of pixels controlled by display driver circuitry. The pixels may have pixel circuits. In liquid crystal display configurations, each pixel circuit may have an electrode that applies electric fields to an associated portion of a liquid crystal layer. In organic light-emitting diode displays, each pixel circuit may have a drive transistor that applies current to an organic light-emitting diode in the pixel circuit. The pixel circuits and display driver circuitry may have thin-film transistor circuitry that includes transistor such as silicon transistors and semiconducting-oxide transistors. Semiconducting-oxide transistors and silicon transistors may be formed on a common substrate. Semiconducting-oxide transistors may have polysilicon layers with doped regions that serve as gates. Semiconducting-oxide channel regions overlap the gates. Transparent conductive oxide and metal may be used to form source-drain terminals that are coupled to opposing edges of the semiconducting oxide channel regions.

A manufacturing method for an array substrate is provided in the present invention. The method comprises: forming a Poly-Silicon layer on a glass substrate; forming heavily doped regions by performing heavily doping and acticvation process at both sides of the Poly-Silicon layer; forming a souce/a drain of a first metal layer growing on the heavily doped region; forming a gate of both a gate insulator and a second metal layer growing sequentially on the Poly-Silicon layer, wherein, a material of the second metal layer is aluminum. The activation technology process can be improved in the present invention to reduce RC delay in metal wires of product and then further to achieve large sizes for products.

A thin film transistor array panel according to an exemplary embodiment of the present invention includes: an insulating substrate; a polycrystal semiconductor layer formed on the insulating substrate; a buffer layer formed below the polycrystal semiconductor layer and containing fluorine; a gate electrode overlapping the polycrystal semiconductor layer; a source electrode and a drain electrode overlapping the polycrystal semiconductor layer and separated from each other; and a pixel electrode electrically connected to the drain electrode.

A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.