Low temperature polysilicon thin film transistor and method for fabricating same

Abstract

The present invention provides a low temperature polysilicon thin film transistor and a fabricating method thereof. According to the method, a laser annealing process is performed to a remained portion of a a-Si layer on a substrate to form a first lightly doped drain (LDD) terminal, a second LDD terminal, a first phosphor material structure and a second phosphor material structure. A gate metal layer is then formed on the remained portion of the a-Si layer. A source metal layer and a drain metal layer are formed on the first doped layer and the second doped layer located at opposite sides of the gate metal layer, respectively. The present invention use the high temperature of the laser annealing process to perform a heat diffusion of phosphor material to form the LDD terminal and the phosphor material structure, the times of photomasks are used is reduced, and the process is simplified.

Claims

1. A method for fabricating a low temperature polysilicon thin film transistor, comprising: depositing an N+ silicon doped layer on a substrate using a material comprising silane, phosphine and hydrogen, and forming a first doped layer and a second doped layer opposite to the first doped layer using a pattern etching process; depositing an amorphous silicon (a-Si) layer on the N+ silicon doped layer, performing a laser annealing process and a pattern etching process to the a-Si layer thereby remaining only a portion of the a-Si layer located in a channel between the first doped layer and the second doped layer; wherein in the laser annealing process, the a-Si layer is crystallized into a polysilicon thin film by laser and a high temperature effect applied to the a-Si layer forms a first lightly doped drain (LDD) terminal between the first doped layer and the polysilicon thin film, a second LDD terminal between the second doped layer and the polysilicon thin film, a first phosphor material structure on the first doped layer and the first LDD terminal, and a second phosphor material structure on the second doped layer and the second LDD terminal; the first LDD terminal and the first phosphor material structure are formed by a high temperature diffusion process of a phosphorus material contained in the first doped layer, and the second LDD terminal and the second phosphor material structure are formed by a high temperature diffusion process of a phosphorus material contained in the second doped layer; forming a gate metal layer on the polysilicon thin film, and forming a source metal layer and a drain metal layer on the first doped layer and the second doped layer located at opposite sides of the gate metal layer, respectively.

2. A method for fabricating a low temperature polysilicon thin film transistor, comprising: depositing an N+ silicon doped layer on a substrate using a material comprising silane, phosphine and hydrogen, and forming a first doped layer and a second doped layer opposite to the first doped layer using a pattern etching process; depositing an amorphous silicon (a-Si) layer on the N+ silicon doped layer, performing a laser annealing process and a pattern etching process to the a-Si layer thereby remaining only a portion of the a-Si layer located in a channel between the first doped layer and the second doped layer; wherein in the step of performing a laser annealing process and a pattern etching process to the a-Si layer, the a-Si layer is crystallized into a polysilicon thin film and a high temperature effect applied to the a-Si layer forms a first lightly doped drain (LDD) terminal between the first doped layer and the polysilicon thin film, a second LDD terminal between the second doped layer and the polysilicon thin film, a first phosphor material structure on the first doped layer and the first LDD terminal, and a second phosphor material structure on the second doped layer and the second LDD terminal; forming a gate metal layer on the polysilicon thin film, and forming a source metal layer and a drain metal layer on the first doped layer and the second doped layer located at opposite sides of the gate metal layer, respectively.

3. The method of claim 2, wherein the first LDD terminal and the first phosphor material structure are formed by a high temperature diffusion process of a phosphorus material contained in the first doped layer, and the second LDD terminal and the second phosphor material structure are formed by a high temperature diffusion process of a phosphorus material contained in the second doped layer.

4. The method of claim 3, wherein an excimer laser annealing process is used in the step of performing a laser annealing process and a pattern etching process to the a-Si layer.

5. The method of claim 3, wherein the phosphorus material contained in the first doped layer and the second doped layer diffuses along a direction towards the polysilicon thin film at a high temperature.

6. The method of claim 2, wherein a relative molecular weight of a phosphorus material contained in the N+ silicon doped layer is equal to 31.

7. The method of claim 2, wherein the method further comprising following step prior to the step of depositing an N+ silicon doped layer on a substrate using a material comprising silane, phosphine and hydrogen, and forming a first doped layer and a second doped layer opposite to the first doped layer using a pattern etching process: controlling the mass ratio of phosphine in the material thereby controlling the resistance of the first and second LDD terminals.

8. The method of claim 3, the method further comprising following step prior to the step of depositing an N+ silicon doped layer on a substrate using a material comprising silane, phosphine and hydrogen, and forming a first doped layer and a second doped layer opposite to the first doped layer using a pattern etching process: controlling the mass ratio of phosphine in the material thereby controlling the resistance of the first and second LDD terminals.

9. The method of claim 4, the method further comprising following step prior to the step of depositing an N+ silicon doped layer on a substrate using a material comprising silane, phosphine and hydrogen, and forming a first doped layer and a second doped layer opposite to the first doped layer using a pattern etching process: controlling the mass ratio of phosphine in the material thereby controlling the resistance of the first and second LDD terminals.

10. The method of claim 2, the method further comprising following step prior to the step of depositing an N+ silicon doped layer on a substrate using a material comprising silane, phosphine and hydrogen, and forming a first doped layer and a second doped layer opposite to the first doped layer using a pattern etching process: controlling the mass ratio of phosphine in the material thereby controlling the resistance of the first and second LDD terminals.

11. The method of claim 5, the method further comprising following step prior to the step of depositing an N+ silicon doped layer on a substrate using a material comprising silane, phosphine and hydrogen, and forming a first doped layer and a second doped layer opposite to the first doped layer using a pattern etching process: controlling the mass ratio of phosphine in the material thereby controlling the resistance of the first and second LDD terminals.

12. The method of claim 6, the method further comprising following step prior to the step of depositing an N+ silicon doped layer on a substrate using a material comprising silane, phosphine and hydrogen, and forming a first doped layer and a second doped layer opposite to the first doped layer using a pattern etching process: controlling the mass ratio of phosphine in the material thereby controlling the resistance of the first and second LDD terminals.

13. The method of claim 2, wherein a yellow light exposure process is used in the step of forming the first doped layer and the second doped layer using a pattern etching process.

14. The method of claim 2, an dehydrogenation process is performed to the a-Si layer in the step of performing a laser annealing process and a pattern etching process to the a-Si layer.

15. A low temperature polysilicon thin film transistor, being fabricated by a method comprising the following steps: depositing an N+ silicon doped layer on a substrate using a material comprising silane, phosphine and hydrogen, and forming a first doped layer and a second doped layer opposite to the first doped layer using a pattern etching process; depositing an amorphous silicon (a-Si) layer on the N+ silicon doped layer, performing a laser annealing process and a pattern etching process to the a-Si layer thereby remaining only a portion of the a-Si layer located in a channel between the first doped layer and the second doped layer; wherein in the laser annealing process, the a-Si layer is crystallized into a polysilicon thin film and a high temperature effect applied to the a-Si layer forms a first lightly doped drain (LDD) terminal between the first doped layer and the polysilicon thin film, a second LDD terminal between the second doped layer and the polysilicon thin film, a first phosphor material structure on the first doped layer and the first LDD terminal, and a second phosphor material structure on the second doped layer and the second LDD terminal; forming a gate metal layer on the polysilicon thin film, and forming a source metal layer and a drain metal layer on the first doped layer and the second doped layer located at opposite sides of the gate metal layer, respectively.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) To illustrate the technical solution provided by embodiments of the present invention more clearly, the figures used to illustrate the embodiments are introduced as follows. Obviously, the listed figures only illustrate some embodiments of the present invention. Those one of ordinarily skilled in the art can also obtain other figures according to the illustrated ones without any creative working.

(2) FIG. 1 is a schematic view illustrating a partial structure of an existing low temperature polysilicon thin film transistor;

(3) FIG. 2 is a flow chart of a method for fabricating a low temperature polysilicon thin film transistor according to one embodiment of the present invention;

(4) FIGS. 3 to 6 are schematic views of the fabricating method of FIG. 2, wherein FIG. 6 is a schematic view illustrating a partial structure of a low temperature polysilicon thin film transistor obtained from the method of FIG. 2.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(5) The technical details of embodiments of the present invention are described clearly and completely with the reference to the figures. Obviously, the described embodiments are only a part of the embodiments, and are not all the embodiments. Based upon these described embodiments, one of ordinarily skilled in the art can obtain other embodiments without any creative working, and these obtained embodiments should also be included in the scope of the present invention.

(6) Referring to FIG. 2, FIG. 2 is a flow chart of a method for fabricating a low temperature polysilicon thin film transistor according to one embodiment of the present invention. The method of the present embodiment includes the following steps.

(7) Step S100, depositing an N+ silicon doped layer on a base layer using a material comprising silane, phosphine and hydrogen, and forming a first doped layer and a second doped layer opposite to the first doped layer using a pattern etching process.

(8) In the step S100, as shown in FIG. 3, the base layer includes a substrate, a SiNx layer and a SiOx layer. The methods or processes used to form the base layer can be any suitable methods in the exiting art can be understood by one of ordinarily skilled in the art, and the methods or processes are not limited.

(9) It is not difficult to understand that molecular formula of silane, phosphine and hydrogen, which are used in the present embodiment, are SiH4, PH3 and H2, respectively. These gases are used as the gas to depositing the film in the present embodiment. However, the material can further include other compositions. In addition, the mass ratio of silane, phosphine and hydrogen in the material gas can be adjusted according to the process requirements.

(10) The pattern etching process in the present embodiment can use the commonly known yellow light exposure and etching process, and is not further described here. The first doped layer and the second doped layer, for example, are the two N+ silicon doped layer opposite to each other as shown in FIG. 3.

(11) Step S101, depositing an amorphous silicon (a-Si) layer on the N+ silicon doped layer, performing a laser annealing process and a pattern etching process to the a-Si layer thereby remaining only a portion of the a-Si layer located in a channel between the first doped layer and the second doped layer, a high temperature effect applied to the remained portion of the a-Si layer by the laser annealing forming a first lightly doped drain (LDD) terminal between the first doped layer and the remained portion of the a-Si layer, a second LDD terminal between the second doped layer and the remained portion of the a-Si layer, respectively, a first phosphor material structure on the first doped layer and the first LDD terminal, and a second phosphor material structure on the second doped layer and the second LDD terminal.

(12) It is to be noted that, as shown in FIG. 4, the first LDD terminal and the first phosphor material structure P31 are formed by the heat diffusion of the phosphor material contained in the first N+ silicon doped layer at a high temperature, the second LDD terminal and the second phosphor material structure P31 are formed by the heat diffusion of the phosphor material contained in the first, second N+ silicon doped layer at a high temperature. It is not difficult to understand that the relative molecular weight of the phosphor material contained in the N+ silicon doped layer is 31. Since the phosphor material contained in the N+ silicon doped layer diffuses rapidly at a high temperature, and thus the existing ion implantation process is not required now.

(13) To perform the laser annealing and the pattern etching process to the a-Si layer, an excimer laser annealing processed is preferred in the present embodiment. Specifically, the a-Si layer is recrystallized into a polysilicon thin film (the structure between the two LDD terminals) by the laser annealing process. As shown in FIG. 4, the phosphor material contained in the first doped layer and the second doped layer diffuse along a direction towards the polysilicon thin film, thereby forming the first, second LDD terminals and the first, second phosphor material structure P31.

(14) Prior to the annealing process, the present embodiment may further include a dehydrogenation process to the a-Si layer.

(15) It is to be noted that, prior to the step 100, the mass ratio of phosphine in the material gas can be controlled to control the resistance of the first LDD terminal and the second LDD terminal. In other words, by controlling the mass ratio of phosphine in the material gas, the phosphor concentration and the volume of obtained structure can be controlled to obtain better structure and performance.

(16) Step S102, forming a gate metal layer on the remained portion of the a-Si layer, and forming a source metal layer and a drain metal layer are formed on the first doped layer and the second doped layer located at opposite sides of the gate metal layer, respectively.

(17) In the step S102, as shown in FIGS. 5 and 6, a gate insulator layer comprised of SiNx and a gate electrode layer comprised of a metal material are formed to obtain the gate metal layer, then an inter-layer dielectric (ILD) layer comprised of SiOx and SiNx can also be formed (not shown).

(18) The source metal layer, for example, is the source layer as shown in FIG. 6, and the drain metal layer is the drain layer as shown in FIG. 6

(19) According to the process provided in the above embodiment, the LDD terminal and the phosphor material structure are formed automatically by a phosphor diffusion of the phosphor material contained in the N+ silicon doped layer when the high temperature of the laser annealing process is applied to the N+ silicon doped layer. The times of using photomasks are reduced, and the fabricating process is simplified.

(20) The embodiment of the present invention reduces two ion implantation processes and corresponding photomasks. The process complexity is reduced, the manufacturing cost is reduced, and the production efficiency is improved.

(21) Referring to FIG. 6, another embodiment of the present invention provides a low temperature polysilicon thin film transistor that can be fabricated by method according to any one of the above embodiments.

(22) In the present embodiment, the low temperature polysilicon thin film transistor includes, but not limited to, a base layer (comprising a substrate layer, a SiNx layer and a SiOx layer sequentially stacked together), oppositely disposed first doped layer and second doped layer, the first, second LDD terminal, the first, the second phosphor material structure P31, the gate metal layer, the source metal layer and the drain metal layer. The fabricating process of the structure can be referred back to the description of the above embodiments, which can be reasonably understood by one of ordinarily skilled in the art, and thus the process is not further described further.

(23) The low temperature polysilicon thin film transistor of the present embodiment can be used in an organic light emitting diode display.

(24) Similarly, the first, second LDD terminals and the first, second phosphor material structures P31 are formed automatically by a phosphor diffusion of the phosphor material contained in the N+ silicon doped layer when the high temperature of the laser annealing process is applied to the N+ silicon doped layer. The structure is simple and the fabricating process is also simple. In detail, the present embodiment reduces two ion implantation processes and corresponding photomasks. The process complexity is reduced, the manufacturing cost is reduced, and the production efficiency is improved.

(25) The above description is only embodiment of the present invention, and is not used to limit the scope of the present invention. Any equivalent structure or equivalent flow alternatives made from the specification and figures of the present invention, such as combination of different embodiments, or direct or indirect application of the present invention into other related fields, should be included in the scope of the present invention.