Proposed is a power semiconductor device and, more particularly, to a power semiconductor device that prevents a decrease in total current amount due to an increase in the length of a current movement path by ensuring that a P-TOP region formed in a resistance unit is spaced apart from a field oxide film thereabove, thereby forming a current path between the P-TOP region and the field oxide film.

A semiconductor device includes a semiconductor substrate in which a first region having a freewheeling diode arranged therein, second regions having an IGBT arranged therein, and a withstand-voltage retention region surrounding the first region and the second regions in plan view are defined. The semiconductor substrate has a first main surface and a second main surface. The semiconductor substrate includes an anode layer having a first conductivity type, which is arranged in the first main surface of the first region, and a diffusion layer having the first conductivity type, which is arranged in the first main surface of the withstand-voltage retention region adjacently to the anode layer. A first trench is arranged in the first main surface on a side of the anode layer with respect to a boundary between the anode layer and the diffusion layer.

A three-dimensional carrier stored trench IGBT and a manufacturing method thereof are provided. A P-type buried layer and a split gate electrode with equal potential to an emitter metal is introduced on the basis of the traditional carrier stored trench IGBT, which can effectively eliminate the influence of an N-type carrier stored layer on breakdown characteristics of the device through the charge compensation, and at the same time can reduce the on-state voltage drop and improve the trade-off relationship between the on-state voltage drop Vceon and the turn-off loss Eoff. The split gate electrodes is introduced in the Z-axis direction, so that the gate electrodes are distributed at intervals. Therefore, the channel density is reduced. The turning on of the parasitic PMOS has a potential-clamping effect on the NMOS channel, so that the saturation current can be reduced and a wider short-circuit safe operating area (SCSOA) can be obtained.

Provided is a semiconductor device with a transistor portion and a diode portion, including a drift region of a first conductivity type and a front surface side electrode provided above a semiconductor substrate. The transistor portion may have a base region of a second conductivity type provided above the drift region; a trench contact portion provided on a front surface of the semiconductor substrate; and a first plug region of a second conductivity type with a higher doping concentration than the base region, under the trench contact portion. The diode portion may have an anode region of a second conductivity type provided above the drift region; and a second plug region of a second conductivity type with a higher doping concentration than the anode region. The second plug region may contact the front surface side electrode in a position shallower than the first plug region.

A semiconductor device includes an emitter, a first base encircling the emitter, a first collector encircling the emitter and the first base, a second base encircling the emitter, the first base and the first collector, and a second collector encircling the second base. The first collector is separated from the emitter by the first base, and the second collector is separated from the emitter, the first base and the first collector by the second base. The emitter, the first base, the first collector, the second base and the second collector form a concentric pattern.

A device includes a substrate, a drift region in the substrate, a base region above the drift region; a first high concentration region selectively formed in a part on a surface side of the base region and having a concentration higher than the drift region; a trench portion formed in a front surface of the substrate and including extending portions; and mesa portions between the extending portions. The mesa portions includes first mesa portions having the first high concentration region and second mesa portions not having the first high concentration region, the trench portion includes a first trench portion having an first conductive portion (a gate conductive portion) and adjacent to the first mesa portion, a second trench portion having the first conductive portion and adjacent to the second mesa portion, and a third trench portion having an second conductive portion and adjacent to the first or second mesa portion.

A semiconductor device include a first semiconductor layer with a first doping concentration. A second semiconductor layer has a second doping concentration and has a first surface and a second opposing surface. The second doping concentration is higher than the first doping concentration. The first surface of the second semiconductor layer is in contact with the first semiconductor layer. A contact is on the second surface of the second semiconductor layer. The contact includes a metal and a semiconductor.

A semiconductor device includes an insulating layer (IFL) on a semiconductor substrate (SUB), a conductive film (PL) on the insulating layer (IFL), an interlayer insulating film (IL) covering the conductive film (PL), a contact hole (CH1) in the interlayer insulating film (IL), the conductive film (PL) and the insulating layer (IFL), and a plug (PG1) embedded in the contact hole (CH1). A side surface of the interlayer insulating film (IL) is separated from a side surface of the conductive film (PL) to expose a part of an upper surface of the conductive film (PL), and a side surface of the insulating layer (IFL) is separated from the side surface of the conductive film (PL) to expose a part of a lower surface of the conductive film (PL). A distance (L1) from the lower surface of the conductive film (PL) to the bottom of the contact hole (CH1) is longer than a distance (L2) from the side surface of the conductive film (PL) to the side surface of the interlayer insulating film (IL).

A power semiconductor device includes a plurality of gate electrodes configured to be recessed from a first surface of a semiconductor substrate to a second surface of the semiconductor substrate, the second surface being opposite to the first surface, an emitter region configured to make contact with a trench and the first surface, being provided between respective ones of the plurality of gate electrodes, and including impurities of a first conductive type, a collector region configured to make contact with the second surface, and including second impurities of a second conductive type opposite to the first conductive type, a floating region extending toward the second surface in an extension direction of the trench while surrounding a bottom surface of the trench, and including the second impurities, and a trench emitter region interposed between the plurality of gate electrodes in the trench.

Disclosed examples include integrated circuits and bipolar transistors with a first region of a first conductivity type in a substrate, a collector region of a second conductivity type disposed in the substrate, and a base region of the first conductivity type extending into the first region. A first emitter region of the second conductivity type extends into the first region and includes a lateral side spaced from and facing the base region. A second emitter region of the second conductivity type extends downward into the first region, abutting the top surface and an upper portion of the first lateral side of the first emitter region to mitigate surface effects and gain degradation caused by hydrogen injection from radiation to provide a radiation hardened bipolar transistor.