A semiconductor device includes a plurality of first trenches each having a stripe-shape, extending in parallel to each other, a first mesa region, a second mesa region, a first interlayer insulating film covering the first mesa region and the second mesa region, and a first contact hole penetrating the first interlayer insulating film to the first mesa region, and extending along a longitudinal direction of the first trenches. The first mesa region includes emitter regions of a first conductivity type periodically provided along the longitudinal direction of the first trenches in a plan view, contact regions of a second conductivity type provided such that each of the emitter regions is interposed between the contact regions along the longitudinal direction in the plan view, and a base region of the second conductivity type provided immediately below the emitter regions and the contact regions.

A bipolar junction transistor (BJT) may include a substrate defining a collector region therein. A first superlattice may be on the substrate including a plurality of stacked groups of first layers, with each group of first layers including a first plurality of stacked base semiconductor monolayers defining a first base semiconductor portion, and at least one first non-semiconductor monolayer constrained within a crystal lattice of adjacent first base semiconductor portions. Furthermore, a base may be on the first superlattice, and a second superlattice may be on the base including a second plurality of stacked groups of second layers, with each group of second layers including a plurality of stacked base semiconductor monolayers defining a second base semiconductor portion, and at least one second non-semiconductor monolayer constrained within a crystal lattice of adjacent second base semiconductor portions. An emitter may be on the second superlattice.

A device and methods of forming the same are described. The device includes a substrate and a first bipolar junction transistor (BJT) disposed over the substrate. The first BJT includes a first base region, a first emitter region, and a first collector region. The device further includes a second BJT disposed over the substrate adjacent the first BJT, and the second BJT includes a second base region, a second emitter region, and a second collector region. The device further includes an interconnect structure disposed over the first and second BJTs, and the interconnect structure includes a first conductive line electrically connected to the first emitter region and the second base region and a second conductive line electrically connected to the first collector region and the second collector region.

Provided is a semiconductor device including a gate trench portion and a first trench portion adjacent to the gate trench portion. The device may include a first conductivity type drift region provided in a semiconductor substrate, a second conductivity type base region provided above the drift region, a first conductivity type emitter region provided above the base region and having a doping concentration higher than that of the drift region, and a second conductivity type contact region provided above the base region and having a doping concentration higher than that of the base region. The contact region includes a first contact portion provided on a front surface of the substrate, and a second contact portion having a doping concentration different from that of the first contact portion and provided alternately with the first contact portion in a trench extending direction on a side wall of the first trench portion.

Provided is a semiconductor device including a drift region, a base region, two trench portions and a mesa portion, wherein at least one of the two trench portions is a gate trench portion, the mesa portion includes: a first conductivity type emitter region provided to be exposed on an upper surface of the mesa portion; a second conductivity type contact region provided to be exposed on the upper surface of the mesa portion alternately with the emitter region in an extending direction; and a second conductivity type connecting region with a higher doping concentration than the base region, wherein the connecting region is provided to overlap with the emitter region in a top view, is arranged apart from the gate trench portion, is arranged below the upper surface of the mesa portion, and connects two of the contact regions sandwiching the emitter region in the extending direction.

The disclosure provides an isolation stack for a bipolar transistor (BT), and related methods. A structure of the disclosure includes a first isolation layer on a subcollector. A first air gap is between the first isolation layer and a collector of a BT. A second isolation layer is on the first isolation layer and adjacent an intrinsic base of the BT. A third isolation layer is on the second isolation layer, vertically between the second isolation layer and an extrinsic base of the BT. A second air gap is adjacent the third isolation layer and below the extrinsic base.

IGBT includes an n-type drift layer, an n-type accumulation layer provided on the upper surface of the drift layer having higher impurity concentration than the drift layer, a base layer provided on the upper surface of the accumulation layer, a gate electrode embedded inside a striped gate trench penetrating the base layer and the storage layer through a gate insulating film, and a dummy electrode embedded inside a dummy trench provided to face the gate trench across the base layer and the accumulation layer through a dummy insulating film. The base layer has a p-type active base region and a p-type floating base region arranged alternately in the extending direction of the gate trench, and an n-type base isolation region isolating the active base region and the floating base region.

A semiconductor device include a first semiconductor layer with a first doping concentration. A second semiconductor layer has a second doping concentration and has a first surface and a second opposing surface. The second doping concentration is higher than the first doping concentration. The first surface of the second semiconductor layer is in contact with the first semiconductor layer. A contact is on the second surface of the second semiconductor layer. The contact includes a metal and a semiconductor.

Bipolar junction devices, and methods and switches using same. At least one example is a bipolar junction device that includes a lower collector-emitter defined by a lower N-type region disposed within a substrate of N-type material, a lower base defined by a lower P-type region disposed within the substrate, and an upper collector-emitter. The upper collector-emitter includes an upper P-type region disposed within the substrate and a metal layer disposed on an upper surface of the substrate. A first portion of the metal layer is electrically coupled to the upper P-type region and a second portion of the metal layer is electrically coupled to the substrate. The second portion is displaced from the first portion.

To realize a highly reliable IGBT that suppresses the bipolar degradation by preventing the occurrence of a defect on a boundary between a contact region and a silicide layer. As a means to realize the above, a semiconductor device includes: a collector region that is formed on a lower surface of a semiconductor substrate and forms an IGBT; and a collector electrode that is formed on a lower surface of the collector region via a silicide layer. The collector region and the silicide layer contains aluminum, first metal being more easily bondable to silicon than aluminum, and second metal being more easily bondable to carbon than aluminum.