A semiconductor device including: a semiconductor substrate a semiconductor element is formed; a first electrode layer stacked on the semiconductor substrate and connected to the semiconductor element; a first insulation film stacked on an upper face of the first electrode layer; and a second electrode layer stacked over the first electrode layer and the first insulation film, the second electrode layer including a material having a mechanical strength that is higher than a mechanical strength of a material included in the first electrode layer; wherein a groove portion is provided from the upper face in a direction toward a lower face of the first electrode layer, a protrusion portion protruding into the groove portion is provided on a lower face of the second electrode layer, and a lower end of the protrusion portion is positioned below the center position in a thickness direction of the first electrode layer.

Disclosed is a transistor device. In an embodiment, the transistor device includes a plurality of transistor cells and a source electrode. Each of the transistor cells includes: a source region of a first doping type; a body region of a second doping type complementary to the first doping type and adjoining the source region; a gate electrode adjacent to the body region, dielectrically insulated from the body region by a gate dielectric, and arranged in a gate trench extending from a first surface of a semiconductor body into the semiconductor body; and a body contact region adjoining the body region and electrically connected to the source electrode. A distance between the body contact region and the gate dielectric is less than 300 nanometers.

Disclosed is a method for forming electrodes, a semiconductor device, and a semiconductor wafer. The semiconductor wafer includes: a plurality of semiconductor bodies and kerf regions arranged between the semiconductor bodies; at least one device electrode arranged above at least one of the semiconductor bodies; and at least one kerf electrode arranged above at least one of the kerf regions. The at least one device electrode includes a first device electrode layer patterned from a first electrically conducting layer and a second device electrode layer patterned from a second electrically conducting layer different from the first electrically conducting layer. The at least one kerf electrode includes a first kerf electrode layer patterned from the first electrically conducting layer and is devoid of a second kerf electrode layer.

An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted.

A voltage-controlled switching device includes a drain/drift structure formed in a semiconductor portion with a lateral cross-sectional area A.sub.Q, a source/emitter terminal, and an emitter channel region between the drain/drift structure and the source/emitter terminal. A resistive path electrically connects the source/emitter terminal and the emitter channel region. The resistive path has an electrical resistance of at least 0.1 m*cm.sup.2/A.sub.Q.

A memory device includes a first etch stop layer, an etch stop pattern, a second etch stop layer, a plurality of stacks and a first conductive pillar. The etch stop pattern is disposed in the first etch stop layer. The second etch stop layer is disposed on the first etch stop layer and the etch stop pattern, wherein a material of the etch stop pattern is different from a material of the first etch stop layer and a material of the second etch stop layer. The stacks are disposed on the second etch stop layer. The first conductive pillar is disposed between the stacks, wherein the first conductive pillar extends along the stacks and the second etch stop layer to be in physical contact with the etch stop pattern.

Microelectronic devices include a tiered stack having vertically alternating insulative and conductive structures. A first series of stadiums is defined in the tiered stack within a first block of a dual-block structure. A second series of stadiums is defined in the tiered stack within a second block of the dual-block structure. The first and second series of stadiums are substantially symmetrically structured about a trench at a center of the dual-block structure. The trench extends a width of the first and second series of stadiums. The stadiums of the first and second series of stadiums have opposing staircase structures comprising steps at ends of the conductive structures of the tiered stack. Conductive source/drain contact structures are in the stack and extend substantially vertically from a source/drain region at a floor of the trench. Additional microelectronic devices are also disclosed, as are methods of fabrication and electronic systems.

A semiconductor device includes an annular semiconductor fin over a semiconductor substrate, a first bottom source/drain structure within the annular semiconductor fin, a second bottom source/drain structure surrounding the annular semiconductor fin, a first silicide layer, a second silicide layer, a first gate structure, a second gate structure, a top source/drain structure, and a contact structure over the top source/drain structure. The first silicide layer and the second silicide layer are over the first bottom source/drain structure and the bottom second source/drain structure, respectively. The first gate structure and the second gate structure are over the first silicide layer and the second silicide layer, respectively. The contact structure includes a lower contact, a middle contact over the lower contact, and an upper contact over the middle contact. A width of the upper contact is greater than a width of the middle contact.

An electronic device and a manufacturing method are provided. The electronic device includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip, and is electrically connected to the first semiconductor chip by hybrid bonding. The third semiconductor chip is stacked on the second semiconductor chip, and is electrically connected to the second semiconductor chip through a plurality of bumps.

A semiconductor device, including: a drift layer of a first conductivity type provided in a semiconductor base; a base layer of a second conductivity type provided in the semiconductor base at a front surface side thereof; a plurality of first trenches provided in the semiconductor base at a front surface side thereof, and having a plurality of first portions extending in a first direction to form a striped pattern; a second trench provided in the semiconductor base at a front surface side thereof, and having a plurality of second portions extending parallel to the first portions; a plurality of gate electrodes respectively provided in the first trenches; and a diode electrode provided in the second trench. The diode electrode includes: a plurality of inner electrodes provided in the second portions, and an outer electrode connecting the inner electrodes and surrounding ends of the first portions in a plan view.