Disclosed is an optimal structure that improves the spatial arrangement efficiency of electrodes and further increases luminous efficacy by designing the shape and structure of photo-device portions and controlling open areas. In particular, provided is a full-color RGB pixel that exhibits excellent reproducibility over a large area and can be mass-produced by forming a plurality of photo-device layers, each including an active layer and a common semiconductor layer in a vertical direction, and forming a plurality of photo-device portions in a horizontal direction on a substrate by selective etching and opening processes.

In a light-emitting element including a first InAs layer that is undoped or doped with an n-type dopant; an active layer including one or more InAs.sub.ySb.sub.1-y layers (0<y<1); and a second InAs layer doped with a p-type dopant, an Al.sub.xIn.sub.1-xAs electron blocking layer (0.05x0.40) with a thickness of 5 nm to 40 nm is provided between the active layer and the second InAs layer.

A display device and a method for fabrication thereof are provided. A display device includes a plurality of pixel electrodes spaced from each other on a substrate, a plurality of light emitting elements respectively located on the plurality of pixel electrodes, a common electrode layer on the plurality of light emitting elements, and an emission defining layer defining emission areas in which the plurality of light emitting elements are located, wherein the emission defining layer is in contact with a side surface of each of the plurality of light emitting elements and surrounds the side surface of each of the plurality of light emitting elements.

A micro-light emitting diode (micro-LED) wafer includes a substrate, an n-type semiconductor layer grown on the substrate, an active region grown on the n-type semiconductor layer and configured to emit visible light, and a p-type semiconductor layer grown on the active region. The active region includes a compressive-strained quantum well layer and compressive-strained quantum barrier layers. At least one of the p-type semiconductor layer or the n-type semiconductor layer includes a tensile-strained layer having a thickness greater than about 50 nm, such that the tensile-strained layers can counter the compressive strain of the active region, thereby reducing the overall strain and bow of the micro-LED wafer.

Systems and devices describe an augmented-reality glasses having a plurality of panels of light emitters arranged to form an array of light emitters, collimation optics for collimating light received from the array of light emitters, an optical coupler for receiving the collimated light, and a waveguide for display of augmented-reality content to a wearer of the augmented-reality glasses. In some embodiments, the array of light emitters includes light emitters generating three colors, each panel of the plurality of panels of light emitters having light emitters generating a same color, and each panel of the plurality of panels of light emitters positioned on a surface of a semiconductor with at least one integrated circuit. The array of light emitters can be two-dimensional array of light emitters arranged on a common plane and characterized by a pitch that is less than 2 m.

A method for manufacturing a flip-chip light emitting diode includes providing a first substrate; performing an epitaxial process to form a semiconductor structure on the first substrate, and the semiconductor structure includes a current conductive layer with a bonding surface and defines a first electrode projection area and a second electrode projection area; performing a diffusion process toward the bonding surface by a diffusion material to form at least one path area with a high doping concentration in the current conductive layer; performing a bonding process to bond a second substrate to the bonding surface; and removing the first substrate and forming a first electrode and a second electrode on a side of the semiconductor structure adjacent to the first substrate. A position of the first electrode corresponds to the first electrode projection area, and a position of the second electrode corresponds to the second electrode projection area.

A nanorod light emitting device, a method of manufacturing the same, and a display apparatus including the nanorod light emitting device are provided. The nanorod light emitting device includes a first semiconductor layer doped with a first conductivity type, a light emitting layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the light emitting layer and doped with a second conductivity type that is electrically opposite to the first conductivity type, wherein a distance between a lower surface of the first semiconductor layer and an upper surface of the second semiconductor layer is in a range of about 2 m to about 10 m, wherein a difference between a diameter of the upper surface of the second semiconductor layer and the lower surface of the first semiconductor layer is 10% or less of a diameter of the upper surface of the second semiconductor layer.

An optoelectronic device including one or a plurality of light-emitting diodes, each light-emitting diode including a three-dimensional semiconductor element, an active area resting on the three-dimensional semiconductor element and a stack of semiconductor layers covering the active area, the active area including a plurality of quantum wells, said stack being in mechanical contact with a plurality of quantum wells.

A vertical thin-film (VTF) light emitting diode (LED) having embedded contacts is described. The vertical thin-film (VTF) light emitting diode (LED) having embedded contacts has structure where the metal layer constitutes both bondpad(s) and associated electric contact to the semiconductor. The metal layer is embedded and, hence, no longer blocking light from the light emitting surface. The vertical thin-film (VTF) light emitting diode (LED) having embedded contacts comprises a plurality of group III-V semiconductor material layers, including binary, ternary, and quaternary alloys of gallium (Ga), aluminum (Al), indium (In), and phosphorus (P) and a multiple quantum well layer on a substrate. At least one ne of the plurality of group III-V semiconductor material layers comprise an aluminum indium phosphide (AlInP) layer or a low confinement layer (LCL) comprising aluminum indium gallium phosphide (AlInGaP).

A multi-active area semiconductor structure and a method for manufacturing same. The multi-active area semiconductor structure includes: a (2k1).sup.th common confining layer arranged between a k.sup.th active layer and a k.sup.th tunnel junction and in contact with the k.sup.th tunnel junction; and a 2k.sup.th common confining layer arranged between the k.sup.th active layer and a (k+1).sup.th tunnel junction and in contact with the k.sup.th tunnel junction, where a forbidden band width of a k.sup.th quantum well layer is less than both a forbidden band width of a k.sup.th first-semiconductor layer and a forbidden band width of a k.sup.th second-semiconductor layer; a total thickness of the (2k1).sup.th common confining layer and the 2k.sup.th common confining layer is greater than a critical optical field coupling thickness and less than or equal to twice the critical optical field coupling thickness; and a thickness of the k.sup.th quantum well layer is less than or equal to 1/10 of a thickness of the (2k1).sup.th common confining layer, and the thickness of the k.sup.th quantum well layer is less than or equal to 1/10 of a thickness of the 2k.sup.th common confining layer. The multi-active area semiconductor structure has effectively improved light-emission efficiency and reduced optical field crosstalk.