The present disclosure relates to a HEMT, which comprises a vertical interface; a channel layer disposed outside of the vertical interface; a channel supply layer disposed outside of the channel layer, wherein a vertical 2 DEG is formed in the channel layer adjacent to an interface between the channel layer and the channel supply layer; a first electrode configured to be electrically connected to the vertical 2 DEG; a second electrode configured to be electrically connected to the vertical 2 DEG; a gate electrode disposed outside of the channel supply layer. The present disclosure also relates to a method of manufacturing a HEMT, which comprises forming a vertical interface; forming a channel layer outside of the vertical interface; forming a channel supply layer outside the channel layer, wherein a vertical 2 DEG is formed in the channel layer adjacent to an interface between the channel layer and the channel supply layer; and forming a first electrode and a second electrode which are electrically connected to the 2 DEG, and a gate electrode which form schottky contact to the 2 DEG.

A semiconductor memory device includes a bit line, a channel pattern including a horizontal channel portion on the bit line and a vertical channel portion vertically protruding from the horizontal channel portion, a word line on the horizontal channel portion and on a sidewall of the vertical channel portion, and a gate insulating pattern between the word line and the channel pattern. The channel pattern includes an oxide semiconductor and includes first, second, and third channel layers sequentially stacked. The first to third channel layers include a first metal, and the second channel layer further includes a second metal different from the first metal. At least a portion of the first channel layer contacts the bit line.

A HEMT device comprises a trench-source contact which includes a first conductive portion and a second conductive portion superimposed on the first conductive portion. The first conductive portion is of a metal material which has a work function value lower than the work function value of the metal material of the second conductive portion.

An insulated gate bipolar transistor includes a P-type group III-V nitride compound layer. An N-type group III-V nitride compound layer contacts a side of the P-type group III-V nitride compound layer. An HEMT is disposed on the N-type group III-V nitride compound layer. The HEMT includes a first group III-V nitride compound layer disposed on the N-type group III-V nitride compound layer. A second group III-V nitride compound layer is disposed on the first group III-V nitride compound layer. A source is embedded within the second group III-V nitride compound layer and the first group III-V nitride compound layer, wherein the source includes an N-type group III-V nitride compound body and a metal contact. A drain contacts another side of the P-type group III-V nitride compound layer. A gate is disposed on the second group III-V nitride compound layer.

Provided is a semiconductor memory device comprising a bit line extending in a first direction, a channel pattern on the bit line and including a first oxide semiconductor layer in contact with the bit line and a second oxide semiconductor layer on the first oxide semiconductor layer, wherein each of the first and second oxide semiconductor layers includes a horizontal part parallel to the bit line and first and second vertical parts that vertically protrude from the horizontal part, first and second word lines between the first and second vertical parts of the second oxide semiconductor layer and on the horizontal part of the second oxide semiconductor layer, and a gate dielectric pattern between the channel pattern and the first and second word lines. A thickness of the second oxide semiconductor layer is greater than that of the first oxide semiconductor layer.

A method of forming a semiconductor device and the structure of the semiconductor device are provided. The manufacturing method includes the following steps of: providing a native substrate; sequentially forming a first nucleation layer, a thick GaN substrate layer, a second nucleation layer, an AlGaN barrier layer, a GaN channel layer and a leakage current stop layer; forming an aperture area through the leakage current stop layer; forming a GaN buffer layer; implanting Mg ions to the GaN buffer layer to form a current blocking layer; forming a GaN drift layer; forming a metallic interlayer on the GaN drift layer and transferring the GaN drift layer on a transferred substrate through the metallic interlayer; removing a semiconductor stack; forming a source contact, a gate contact and a drain contact.

A vertical field-effect transistor. The vertical field-effect transistor has: A first semiconductor layer, which has a p-type conductivity, on or over a drift region; a groove structure which penetrates the first semiconductor layer vertically, the groove structure having at least one side wall on which a field-effect transistor (FET)-channel region is formed, the FET-channel region having a III-V-heterostructure for forming a two-dimensional electron gas at an interface of the III-V-heterostructure; a source-drain electrode which is electroconductively connected to the III-V-heterostructure; and a contact structure at least partially on or over the drift region, which forms a Schottky- or hetero-contact at least with the drift region, the contact structure being electroconductively connected to the source-drain electrode, and at least the region lying vertically between the contact structure and the drift region being free of the first semiconductor layer.

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.

A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer provided above the substrate; a second nitride semiconductor layer of p-type conductivity provided above the first nitride semiconductor layer; a third nitride semiconductor layer and a fourth nitride semiconductor layer that are provided along the inner surface of a first opening and at a portion that is outside the first opening and above the second nitride semiconductor layer, the first opening passing through the second nitride semiconductor layer; a gate electrode; a source electrode; and a drain electrode. The third nitride semiconductor layer includes: a bottom portion provided along the bottom surface of the first opening; and an outer edge portion provided outside the first opening. The layer thickness of the bottom portion is less than the layer thickness of the outer edge portion.

A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer of a first conductivity type which is provided above the substrate; a second nitride semiconductor layer which is provided above the first nitride semiconductor layer; an electron transport layer and an electron supply layer which are sequentially provided above the second nitride semiconductor layer; a third nitride semiconductor layer and a gate electrode which are sequentially provided above the electron supply layer; a source electrode; and a drain electrode, the second nitride semiconductor layer includes: a current conducting portion of the first conductivity type which is located below the third nitride semiconductor layer and includes a first impurity; and a current blocking portion which is provided about the current conducting portion, and the concentration of the first impurity in the electron transport layer is lower than the concentration of the first impurity in the current conducting portion.