The present disclosure relates to a semiconductor device and a manufacturing method thereof; wherein the semiconductor device comprises a semiconductor device layer including one or more semiconductor devices; a first electrode interconnection layer disposed on a first side of the semiconductor device layer; one or more first metal pillars disposed on the first side of the semiconductor device layer and electrically connected to the first electrode interconnection layer; a first insulating material disposed around the one or more first metal pillars, wherein the first insulating material is an injection molding material; and a second electrode interconnection layer disposed on a second side opposite to the first side of the semiconductor device layer. In the technical scheme of the present disclosure, the temporary substrate is not required to achieve better support strength and complete the related processes of the semiconductor manufacturing process, which is convenient, convenient and low in cost.

A semiconductor structure includes a substrate, an N+ type gallium nitride epitaxial layer, an N type gallium nitride epitaxial layer and a first AlGaN layer which are sequentially disposed; a P-type gallium nitride epitaxial layer extending from a surface of a side, away from the substrate, of the first AlGaN layer into the N type gallium nitride epitaxial layer; and a second AlGaN layer located on a side, away from the substrate, of the first AlGaN layer and the P-type gallium nitride epitaxial layer. According to technical solutions of the present disclosure, an enhancement mode device with a high threshold voltage can be realized and an on-resistance of the device can be reduced.

There is provided a vertical high-electron-mobility transistor, which may include: a drain contact a nanowire layer arranged on the drain contact and at least one vertical nanowire and a supporting material laterally enclosing the at least one vertical nanowire, a heterostructure arranged on the nanowire layer and comprising an AlGaN-layer and a GaN-layer together forming a heterojunction, at least one source contact in contact with the heterostructure, and a gate contact in contact with the heterostructure, arranged above the at least one vertical nanowire, the at least one vertical nanowire is forming an electron transport channel. Also disclosed is a method for producing same.

A lateral surface gate vertical field effect transistor with adjustable output capacitance is described herein. The lateral surface gate vertical field effect transistor includes both a lateral gate and a trench gate. The lateral gate modulates a surface channel and the trench gate includes a controllable depth. The controllable depth may be varied to advantageously adjust output capacitance.

A semiconductor device including a semiconductor substrate, a lower metal contact disposed upon the semiconductor substrate, a gate structure disposed upon the lower metal contact, an upper metal contact disposed upon the gate structure, and a plurality of semiconductor carriers disposed in contact with both the lower metal contact and the upper metal contact, the plurality of semiconductor carriers disposed in channels passing through the gate structure.

A MOSFET with saturation contact. The MOSFET with saturation contact includes an n-doped source region, a source contact, a contact structure, which extends from the source contact to the n-doped source region, and forms with the source contact a first conductive connection and forms with the n-doped source region a second conductive connection, a barrier layer and an insulating layer. The contact structure includes a section between the first conductive connection and the second conductive connection, which is embedded between the barrier layer and the dielectric layer and is configured in such a way that a two-dimensional electron gas is formed therein.

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.

A nitride semiconductor device includes a substrate, a first nitride semiconductor layer, a first p-type nitride semiconductor layer and a second nitride semiconductor layer disposed sequentially from below; an electron transport layer and an electron supply layer arranged sequentially from below to cover a first opening and the second nitride semiconductor layer, the first opening penetrating through the second nitride semiconductor layer and the first p-type nitride semiconductor layer; a second p-type nitride semiconductor layer or an insulating layer disposed in a position overlapping with a bottom surface of the first opening; a gate electrode disposed in a position overlapping with the second nitride semiconductor layer; a first source electrode disposed to cover a second opening penetrating through the electron supply layer and the electron transport layer; a drain electrode; and a second source electrode disposed above the second p-type nitride semiconductor layer or the insulating layer.

A vertical fin-based field effect transistor (FinFET) device includes an array of FinFETs comprising a plurality of rows and columns of fins, each of the fins having a fin length and a fin width measured laterally with respect to the fin length and including a first fin tip disposed at a first end of the fin; a second fin tip disposed at a second end of the fin opposing the first end; a bridging structure connecting the first fin tip to an adjacent fin; a central region disposed between the first fin tip and the second fin tip and characterized by an electrical conductivity; and a source contact electrically coupled to the central region. The FinFET device also includes a gate region surrounding the fins.