The display panel includes a substrate and a plurality of thin film transistors disposed on the substrate. Each of the thin film transistors includes: a semiconductor layer on the substrate. The semiconductor layer includes a channel portion and conductor portions disposed on both sides of the channel portion. A gate electrode is defined with a first length, the channel portion is defined with a second length, and a ratio of the second length to the first length is greater than 0.7 and is less than or equal to 1.

A semiconductor device with a small occupation area is provided. The semiconductor device includes a first insulating layer, a second insulating layer, and a transistor. The transistor is provided over the first insulating layer and includes a semiconductor layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode. The second insulating layer includes an opening reaching the first insulating layer. The source electrode and the drain electrode are provided over the second insulating layer. The semiconductor layer is provided in contact with a side surface of the second insulating layer in the opening, a top surface of the first insulating layer in the opening, and side surfaces of the source electrode and the drain electrode. The gate insulating layer is positioned over the semiconductor layer, the source electrode, and the drain electrode. The gate electrode overlaps with the opening and is positioned over the gate insulating layer.

The present disclosure provides a display panel including a display area in which subpixels are disposed, and a non-display area outside of the display area in which an image is not displayed, and a display device including the display panel and a driving circuit configured to drive the display panel. The non-display area includes a test area in which a plurality of test transistors are disposed that correspond to a plurality of transistors included in the subpixels. An operating characteristic of the test transistors is detected which is representative of an operating characteristic of the transistors included in the subpixels.

A semiconductor device is provided over a base insulating layer including hydrogen. A first conductive layer, a spacer, and a second conductive layer are provided over the base insulating layer. The spacer and the second conductive layer comprise an opening reaching the first conductive layer in which a metal oxide layer is provided. The metal oxide layer includes a region in contact with the first conductive layer and the second conductive layer. The first conductive layer and the second conductive layer function as one and the other of a source electrode and a drain electrode of the transistor. A gate insulating layer is provided over the metal oxide layer to include a region positioned in the opening. A gate electrode is provided to include a region facing the metal oxide layer with the gate insulating layer between the region and the metal oxide layer in the opening.

An electronic device includes: a substrate; a first transistor disposed on the substrate and having a first operating voltage; and a second transistor disposed on the substrate and having a second operating voltage. The first transistor includes a first semiconductor layer, a first gate, and a first insulating structure. The first insulating structure is disposed between the first semiconductor layer and the first gate. The second transistor includes a second semiconductor layer, a second gate, and a second insulating structure. The second insulating structure is disposed between the second semiconductor layer and the second gate. The first operating voltage is higher than the second operating voltage, and a thickness of the first insulating structure is greater than a thickness of the second insulating structure.

A semiconductor device that can be reduced in size or highly integrated is provided. The semiconductor device includes first and second transistors and first to third conductors. The first transistor includes first and second gate electrodes between which a semiconductor layer of the first transistor is positioned. The second gate electrode is provided over the semiconductor layer of the first transistor to overlap the first gate electrode. The second transistor includes a third gate electrode over a semiconductor layer of the second transistor. The second transistor is stacked over the first transistor. The third gate electrode overlaps the second gate electrode. The first conductor electrically connects a source electrode of the first transistor and a source electrode of the second transistor. The second conductor electrically connects a drain electrode of the first transistor and a drain electrode of the second transistor. The third conductor electrically connects the first gate electrode, the second gate electrode, and the third gate electrode.

An active device substrate includes a substrate, a first semiconductor device and a second semiconductor device. The first semiconductor device and the second semiconductor device are disposed above the substrate. The first semiconductor device includes a first gate, a first semiconductor layer, a first source and a first drain. A first gate dielectric structure is sandwiched between the first gate and the first semiconductor layer. The first gate dielectric structure includes a stack of a portion of a gate dielectric layer and a portion of a ferroelectric material layer. The second semiconductor device is electrically connected to the first semiconductor device and includes a second gate, a second semiconductor layer, a second source and a second drain. Another part of the ferroelectric material layer is sandwiched between the second gate and the second semiconductor layer.

An electronic device includes a first transistor disposed on a substrate and including a first semiconductor pattern and a first gate, and a buffer layer. The buffer layer includes a first part overlapping the first semiconductor pattern in a plan view and having a first thickness, and a second part connected to the first part and having a second thickness, the second thickness and the first thickness being different from each other.

Embodiments of the present application provide an array substrate and a preparation method therefor, and a display panel. The array substrate includes: a substrate; a first semiconductor layer located on one side of the substrate, the first semiconductor layer including a first active portion; a first insulating layer located on a side of the first semiconductor layer facing away from the substrate; a second semiconductor layer located on a side of the first insulating layer facing away from the first semiconductor layer, the second semiconductor layer including a second active portion; wherein a carrier mobility of one of the first active portion and the second active portion is greater than that of the other.

A transistor and a display apparatus including the same are provided. The display apparatus includes a substrate including an active area and a non-active area. A first transistor is disposed in the active area and includes a first gate electrode, a first-a source drain electrode, a first-b source drain electrode, and a first active layer. A first gate insulation layer is disposed between the first gate electrode and the first active layer. The first gate insulation layer includes a first portion, disposed adjacent to an edge outer portion of the first gate electrode and not overlapping the gate electrode, and a second portion, disposed overlapping the first gate electrode. The thickness of the first portion differs from the thickness of a second portion. By adjusting the gate insulation thickness, the structure may help control dopant distribution and enhance the electrical stability and reliability of the first transistor.