A semiconductor device includes a semiconductor structure forming a carrier channel, a barrier layer arranged in proximity with the semiconductor structure, and a set of electrodes for providing and controlling carrier charge in the carrier channel. The barrier layer is at least partially doped by impurities having a conductivity type opposite to a conductivity type of the carrier channel. The material of the barrier layer has a bandgap and thermal conductivity larger than a bandgap and thermal conductivity of material in the semiconductor structure.

A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

A method of manufacturing a semiconductor device includes forming a barrier structure over a substrate. The method further includes forming a channel layer over the barrier structure. The method further includes depositing an active layer over the channel layer. The method further includes forming source/drain electrodes over the channel layer. The method further includes annealing the source/drain electrodes to form ohmic contacts in the active layer under the source/drain electrodes.

Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.

A semiconductor device is disclosed. The semiconductor device includes a substrate and a plurality of devices on the substrate, wherein a first device of the devices includes a first nitride semiconductor layer on the substrate, a second nitride semiconductor layer brought together with the first nitride semiconductor layer to form a first heterojunction interface, between the substrate and the first nitride semiconductor layer, a third nitride semiconductor layer brought together with the second nitride semiconductor layer to form a second heterojunction interface, between the substrate and the second nitride semiconductor layer, and a first contact electrically connected to the first and second heterojunction interfaces.

Methods, systems, and apparatuses for normally-on GaN high electron mobility transistors (HEMT) integration on monolithic p-GaN integrated circuits (ICs) platforms are provided. In particular, the integrated circuit platforms may include both enhancement mode and depletion mode HEMT power devices in monolithically integrated p-GaN power ICs. Exemplary methods may include treating at least one of a plurality of p-GaN gates with an in-situ plasma treatment to deactivate Mg in the p-GaN gate treated and deplete this p-Gan gate of Mg. The depleted p-GaN gate may be the gate for the normally on HEMT in the IC. At least one of the p-GaN gates not exposed to the in-situ plasma pretreatment may be the gate of the normally off HEMT in the IC.

A method for manufacturing nitride semiconductor device includes a second step of forming, on a gate layer material film, a gate electrode film that is a material film of a gate electrode, a third step of selectively etching the gate electrode film to form the gate electrode of a ridge shape, and a fourth step of selectively etching the gate layer material film to form a semiconductor gate layer of a ridge shape with the gate electrode disposed at a width intermediate portion of a front surface thereof. The third step includes a first etching step for forming a first portion from an upper end to a thickness direction intermediate portion of the gate electrode and a second etching step being a step differing in etching condition from the first etching step and being for forming remaining second portion of the gate electrode.

A substrate includes a support structure comprising a polycrystalline ceramic core, a first adhesion layer encapsulating the polycrystalline ceramic core, a barrier layer encapsulating the first adhesion layer, a second adhesion layer coupled to the barrier layer, and a conductive layer coupled to the second adhesion layer. The substrate also includes a bonding layer coupled to the support structure, a substantially single crystal silicon layer coupled to the bonding layer, and an epitaxial semiconductor layer coupled to the substantially single crystal silicon layer.

The present application discloses a planar High-Electron-Mobility Transistor (HEMT), which includes a hetero-junction consisting of a first semiconductor epitaxial layer and a second semiconductor epitaxial layer, and two-dimensional electron gas located at an interface of the hetero-junction; a bottom surface of a gate trench of a trench gate is located at a bottom of the two-dimensional electron gas to cut off the two-dimensional electron gas; when gate-source voltage is higher than or equal to threshold voltage, an inversion layer is formed on a surface of the first semiconductor epitaxial layer covered by side surfaces and a bottom surface of a gate conductive material layer, and the source-end and drain-end two-dimensional electron gas is conducted to enable the device to be on; when the gate-source voltage is lower than the threshold voltage, the source-end and drain-end two-dimensional electron gas is cut off to enable the device to be off.

A semiconductor device according to an embodiment includes: a channel layer; a barrier layer above the channel layer and including a material having an energy band gap different from an energy band gap of the channel layer; a gate electrode above the barrier layer; a gate semiconductor layer between the barrier layer and the gate electrode; a source electrode and a drain electrode that are at both sides of the gate electrode and covering side surfaces of the channel layer and the barrier layer; and a superlattice layer between the barrier layer and the gate semiconductor layer, the superlattice layer including at least one first layer including AlGaN and at least one second layer including GaN, wherein the at least one first layer and the at least one second layer are alternately stacked.