This normally-off mode polarization super junction GaN-based FET has an undoped GaN layer 11, an Al.sub.xGa.sub.1xN layer 12, an island-like undoped GaN layer 13, a p-type GaN layer 14 and a p-type In.sub.yGa.sub.1yN layer 15 which are stacked in order. The FET has a gate electrode 16 on the uppermost layer, a source electrode 17 and a drain electrode 17 on the Al.sub.xGa.sub.1xN layer 12 and a p-type In.sub.zGa.sub.1zN layer 19 and a gate electrode 20 which are located beside one end of the undoped GaN layer 13 on the Al.sub.xGa.sub.1xN layer 12. The gate electrode 20 may be provided on the p-type In.sub.zGa.sub.1xN layer 19 via a gate insulating film. At a non-operating time, n.sub.0n.sub.1<n.sub.2<n.sub.3 is satisfied for the concentration n.sub.0 of the 2DEG 22 formed in the undoped GaN layer 11/the Al.sub.xGa.sub.1xN layer 12 hetero-interface just below the gate electrode 20, the concentration n.sub.1 of the 2DEG 22 just below the gate electrode 16, the concentration n.sub.2 of the 2DEG 22 in the polarization super junction region and the concentration n.sub.3 of the 2DEG 22 in the part between the polarization super junction region and the drain electrode 18.

A micro-electronic device includes a first electronic component and a second electronic component, and a substrate formed of a first semiconductor material for supporting the components. The first component and the second component each include an active layer formed at least partially from a second semiconductor material different from the first semiconductor material. The device further includes, for each of the components, a stack for maintaining electrical voltage, which stack is situated between the substrate and the active layer of the electronic component under consideration and which comprises two layers forming a junction P-N formed from the same semiconductor material as the substrate and which insulates the relevant active layer from the substrate. The assemblies respectively including the first component and the second component and their respective stack for maintaining electrical voltage are separated from each other by a barrier made of electrically insulating material.

The present disclosure relates to a semiconductor device and a manufacturing method thereof; wherein the semiconductor device comprises a semiconductor device layer including one or more semiconductor devices; a first electrode interconnection layer disposed on a first side of the semiconductor device layer; one or more first metal pillars disposed on the first side of the semiconductor device layer and electrically connected to the first electrode interconnection layer; a first insulating material disposed around the one or more first metal pillars, wherein the first insulating material is an injection molding material; and a second electrode interconnection layer disposed on a second side opposite to the first side of the semiconductor device layer. In the technical scheme of the present disclosure, the temporary substrate is not required to achieve better support strength and complete the related processes of the semiconductor manufacturing process, which is convenient, convenient and low in cost.

The embodiment of the present disclosure provides a semiconductor structure and a method for manufacturing thereof, the semiconductor structure includes a substrate and a channel structure at a side of the substrate, and the channel structure includes a first channel layer and a first barrier layer which are sequentially disposed at a side of the substrate; where the semiconductor structure includes a gate region, and a source region and a drain region at both sides of the gate region, the channel structure in the source region is provided with a first groove, and the channel structure in the drain region is provided with a second groove; and two N-type heavily doped layers are in the first groove and the second groove respectively, where a surface of the N-type heavily doped layers away from the substrate has a plurality of V-shaped pits.

A complementary high electron mobility transistor includes an N-type HEMT and an P-type HEMT disposed on the substrate. The N-type HEMT includes a first undoped gallium nitride layer, a first quantum confinement channel, a first undoped group III-V nitride compound layer and an N-type group III-V nitride compound layer disposed from bottom to top. A first gate is disposed on the N-type group III-V nitride compound layer. A first source and a first drain are disposed at two sides of the first gate. The P-type HEMT includes a second undoped gallium nitride layer, a second quantum confinement channel, a second undoped group III-V nitride compound layer and a P-type group III-V nitride compound layer disposed from bottom to top. A second gate is disposed on the P-type group III-V nitride compound layer. A second source and a second drain are disposed at two sides of the second gate.

An apparatus configured to reduce lag includes a substrate; a group III-Nitride back barrier layer on the substrate; a group III-Nitride channel layer on the group III-Nitride back barrier layer; a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer include a higher bandgap than a bandgap of the group III-Nitride channel layer; a source electrically coupled to the group III-Nitride barrier layer; a gate on the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; and a p-region being arranged at or below the group III-Nitride barrier layer. Additionally, at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, an area between the gate and the drain.

The folded channel gallium nitride based field-effect transistor includes: a base layer; a multi-heterojunction layer, including a channel layer and a barrier layer alternatingly stacked from bottom to top on a gallium nitride semi-insulating layer; a gallium nitride control layer on the multi-heterojunction layer and extending from one side of the channel region to at least a part of the groove; a current collapse suppression structure formed on the multi-heterojunction layer on another side of the channel region; a source electrode and a drain electrode that are respectively in contact with two sides of the multi-heterojunction layer on the gallium nitride semi-insulating layer; a gate electrode formed on the multi-heterojunction layer between the source electrode and the gallium nitride control layer; and a connecting structure passing over the gate electrode to electrically connect to the source electrode and the gallium nitride control layer.