This normally-off mode polarization super junction GaN-based FET has an undoped GaN layer 11, an Al.sub.xGa.sub.1-xN layer 12, an island-like undoped GaN layer 13, a p-type GaN layer 14 and a p-type In.sub.yGa.sub.1-yN layer 15 which are stacked in order. The FET has a gate electrode 16 on the uppermost layer, a source electrode 17 and a drain electrode 17 on the Al.sub.xGa.sub.1-xN layer 12 and a p-type In.sub.zGa.sub.1-zN layer 19 and a gate electrode 20 which are located beside one end of the undoped GaN layer 13 on the Al.sub.xGa.sub.1-xN layer 12. The gate electrode 20 may be provided on the p-type In.sub.zGa.sub.1-zN layer 19 via a gate insulating film. At a non-operating time, n.sub.0n.sub.1<n.sub.2<n.sub.3 is satisfied for the concentration n.sub.0 of the 2DEG 22 formed in the undoped GaN layer 11/the Al.sub.xGa.sub.1-xN layer 12 hetero-interface just below the gate electrode 20, the concentration n.sub.1 of the 2DEG 22 just below the gate electrode 16, the concentration n.sub.2 of the 2DEG 22 in the polarization super junction region and the concentration n.sub.3 of the 2DEG 22 in the part between the polarization super junction region and the drain electrode 18.

A semiconductor device includes a semiconductor substrate, an Aluminum Gallium-Nitride (AlGaN) back-barrier layer formed above the semiconductor substrate, and a GaN channel layer formed on the AlGaN back-barrier layer. A two-dimensional hole gas (2DHG) is formed at an interface between the GaN channel layer and the AlGaN back-barrier layer, and a p-type doped region is formed above the semiconductor substrate and next to the GaN channel layer and the AlGaN back-barrier layer. The p-type doped region is configured to provide an ohmic contact for the 2DHG. The p-type doped region comprises Magnesium as a p-type dopant. The p-type doped region comprises one or more hollow chambers extending from the top face of the p-type doped region. The hollow chambers are configured to form an escape path for Hydrogen atoms which are formed during a dopant activation of the p-type doped region during fabrication of the semiconductor device.

A device includes a substrate and a heterostructure supported by the substrate. The heterostructure includes a III-nitride layer and a ferroelectric layer supported by the III-nitride layer. The ferroelectric layer includes a quaternary III-nitride alloy. The quaternary III-nitride alloy includes a Group IIIB element. The ferroelectric layer has a lattice constant greater than a lattice constant of gallium nitride (GaN).

A transistor comprising a gallium nitride layer having a first gate electrode partially penetrating into it, having: a first side coated with a first thickness of a first insulating material and of a second insulating material; and with a second thickness of a conductive material; and a bottom coated with a third thickness, smaller than the first thickness, of the first insulating material.

Semiconductor structures that inhibit the conductivity of parasitic channels are described. In one example, a semiconductor structure includes a substrate, a III-nitride material region over a top surface of the substrate, a first species implanted within at least one region of surface region of the substrate in a first pattern spatially defined across a lateral dimension of the substrate, and a second species implanted within at least one region of the III-nitride material region. The second species can be implanted in a second pattern spatially defined across the lateral dimension of the substrate. The surface region of the substrate includes a parasitic channel. The at least one region of the substrate in which the first species is implanted includes a low-conductivity parasitic channel or is free of the parasitic channel.

An apparatus to address gate lag effect and/or other negative performance includes a substrate; a group III-Nitride buffer layer on the substrate; a group III-Nitride barrier layer on the group III-Nitride buffer layer, the group III-Nitride barrier layer may include a higher bandgap than a bandgap of the group III-Nitride buffer layer; a source electrically coupled to the group III-Nitride barrier layer; a gate electrically coupled to the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; and a p-region being arranged at least in the substrate. In particular, the p-region extends toward a source side of the substrate; and the p-region extends toward a drain side of the substrate.

An embodiment provides a semiconductor device including: a channel layer; a barrier layer disposed on the channel layer and including a material having an energy band gap different from that of the channel layer; a gate semiconductor layer disposed on the barrier layer; a gate structure including a first gate electrode disposed on the gate semiconductor layer and a second gate electrode disposed between the first gate electrode and the gate semiconductor layer, and a source electrode and a drain electrode disposed on both sides of the gate structure and connected to the channel layer, wherein the first gate electrode includes a first curved surface between an upper surface and a side surface of the first gate electrode, and a second curved surface between a lower surface and a side surface of the first gate electrode, and a curvature of the first curved surface is smaller than that of the second curved surface.

An apparatus includes a substrate. The apparatus further includes a group III-nitride buffer layer on the substrate; a group III-nitride barrier layer on the group III-nitride buffer layer, the group III-nitride barrier layer including a higher bandgap than a bandgap of the group III-nitride buffer layer. The apparatus further includes a source electrically coupled to the group III-nitride barrier layer; a gate electrically coupled to the group III-nitride barrier layer; a drain electrically coupled to the group III-nitride barrier layer; and a p-region being at least one of the following: in the substrate or on the substrate below said group III-nitride barrier layer.

Semiconductor devices and methods of forming the same are provided. A method of the present disclosure includes depositing an aluminum nitride layer over a substrate, treating the aluminum nitride layer to convert a top portion of the aluminum nitride layer to an aluminum oxynitride layer, depositing a III-V semiconductor layer on the aluminum oxynitride layer, and forming a gate structure over the III-V semiconductor layer.

A method for manufacturing a semiconductor device includes preparing a first substrate provided with a first pattern on a first surface, and a semiconductor chip having a second surface, and a third surface opposite to the second surface, and including a second pattern provided on the second surface, recognizing the first pattern from a position near the first surface among the first surface and an opposite surface thereof in the first substrate, recognizing the second pattern by transmitting through the semiconductor chip from a position near the third surface among the second surface and the third surface in the semiconductor chip, aligning the semiconductor chip and the first substrate based on a recognition result of the first pattern and the second pattern, and bonding the semiconductor chip to the first substrate so that the second surface faces the first surface.