Embodiments of the present invention are directed to semiconductor electronic devices formed of 2-D van der Waals material whose free charge carrier concentration is determined by adjacent semiconductor's polarization. According to one particular embodiment, a semiconductor electronic device is composed of one or more layers of two dimensional (2-D) van der Waals (VDW) material; and one or more layers of polarized semiconductor material adjacent to the one or more layer of 2-D VDW material. The polarization of the adjacent semiconductor material establishes the free carrier charge concentration of the 2-D VDW material.

A device includes a transistor formed over a substrate. The transistor includes a source structure, a drain structure, and a gate structure. A dielectric layer is formed over the transistor, and a plurality of vias are electrically connected to the source structure. A metal layer is formed over the dielectric layer. The metal layer includes a field plate over the gate structure, a plurality of contact pads over each via, and a plurality of fingers interconnecting each one of the plurality of contact pads to the field plate.

A field effect transistor includes a substrate; a first semiconductor layer, disposed over the substrate; a second semiconductor layer, disposed over the first semiconductor layer, wherein an interface between the first semiconductor layer and the second semiconductor layer has a two-dimensional electron gas; a p+ III-V semiconductor layer, disposed over the second semiconductor layer; and a depolarization layer, disposed between the second semiconductor layer and the p+ III-V semiconductor layer, wherein the depolarization layer includes a metal oxide layer.

A Group III-nitride-based enhancement mode transistor having a heterojunction fin structure and a corresponding semiconductor device are described.

There are disclosed herein various implementations of a III-Nitride bidirectional device. Such a bidirectional device includes a substrate, a back channel layer situated over the substrate, and a device channel layer and a device barrier layer situated over the back channel layer. The device channel layer and the device barrier layer are configured to produce a device two-dimensional electron gas (2DEG). In addition, the III-Nitride bidirectional device includes first and second gates formed on respective first and second depletion segments situated over the device barrier layer. The III-Nitride bidirectional device also includes a back barrier situated between the back channel layer and the device channel layer. A polarization of the back channel layer of the III-Nitride bidirectional device is substantially equal to a polarization of the device channel layer.

A semiconductor apparatus includes an electron transit layer formed of a nitride semiconductor over a substrate; an electron supply layer formed of a nitride semiconductor including In over the electron transit layer; a cap layer formed of a nitride semiconductor over the electron supply layer; an insulation film formed over the cap layer; a source electrode and a drain electrode formed over the electron transit layer or the electron supply layer; and a gate electrode formed over the cap layer. A quantum well is formed by the cap layer.

The present invention provides a filed effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first III-V compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first III-V compound layer, and source/drain electrodes are respectively located at each side of the gate electrode and on the first III-V compound layer. According to the present invention, the band width of the barrier layer is greater than that of the first III-V compound layer, and the band curvatures of the barrier layer and the first III-V compound layer are different, therefore, a two dimensional electron gas (2DEG) is formed in the first III-V compound layer near the barrier layer boundary. Since the 2DEG has higher mobility, the performance of the filed effect transistor improved. Besides, the performance of the filed effect transistor also improved due to the structure is a gate-all-around structure.

The present invention provides a method for forming a quantum well device having high mobility and high breakdown voltage with enhanced performance and reliability. A method for fabrication of a Vertical Cylindrical GaN Quantum Well Power Transistor for high power application is disclosed. Compared with the prior art, the method of forming a quantum well device disclosed in the present invention has the beneficial effects of high mobility and high breakdown voltage with better performance and reliability.

Embodiments provide a quantum well device and the method for forming this device with high mobility and higher punch through voltages. For forming the quantum well device, a buffer layer can be formed on a patterned substrate of a quantum well device. A fin-like structure can be formed through an etching process performed to the buffer layer. A quantum well layer, a barrier layer, a cover layer and a dielectric layer can be successively deposited on the buffer layer and surface of the fin-like structure. A metal layer can then be formed on the surface of the said dielectric layer. Metal gate electrode and gate dielectric layer can be formed on the metal layer and dielectric layer. The cover layer, the barrier layer and the quantum well can then be etched to form recessed source and drain regions. Such a quantum well device can have better performance and reliability.

The disclosure relates to a method for manufacturing an Au-free ohmic contact for an III-nitride (III-N) device on a semiconductor substrate and to a III-N device obtainable therefrom. The III-N device includes a buffer layer, a channel layer, a barrier layer, and a passivation layer. A 2DEG layer is formed at an interface between the channel layer and the barrier layer. The method includes forming a recess in the passivation layer and in the barrier layer up to the 2DEG layer, and forming an Au-free metal stack in the recess. The metal stack comprises a Ti/Al bi-layer, with a Ti layer overlying and in contact with a bottom of the recess, and a Al layer overlying and in contact with the Ti layer. A thickness ratio of the Ti layer to the Al layer is between 0.01 to 0.1. After forming the metal stack, a rapid thermal anneal is performed. Optionally, prior to forming the Ti/Al bi-layer, a silicon layer may be formed in contact with the recess.