Systems and methods for performing word line pulse techniques in magnetoelectric junctions in accordance with embodiments of the invention are disclosed. In one embodiment, a magnetoelectric random access memory (MeRAM) circuit, including, a plurality of voltage controlled magnetic tunnel junction bits (MEJs) each magnetoelectric junction connected to the drain of an MOS transistor, the combination including three terminals, each connected to a bit, source, and at least one word line, in an array, and a driver circuit, including a bit line driver, and a word line driver the bit line driver, the driver circuit generates voltage pulses for application to the magnetoelectric junction bit, the output of the driver circuit is connected to the word line, which in turn is connected to the gate of the MOS access transistor in each MeRAM cell, thereby generating a square voltage pulse across the magnetoelectric junction bit.

An integrated circuit which enables lower cost yet provides superior performance compared to standard silicon integrated circuits by utilizing thin film transistors (TFTs) fabricated in BEOL. Improved memory circuits are enabled by utilizing TFTs to improve density and access in a three dimensional circuit design which minimizes die area. Improved I/O is enabled by eliminating the area on the surface of the semiconductor dedicated to I/O and allowing many times the number of I/O available. Improved speed and lower power are also enabled by the shortened metal routing lines and reducing leakage.

Embodiments are directed to a magnetic tunnel junction (MTJ) memory cell that includes a reference layer formed from a perpendicular magnetic anisotropy (PMA) reference layer and an interfacial reference layer. The MTJ further includes a free layer and a tunnel barrier positioned between the interfacial reference layer and the free layer. The tunnel barrier is configured to enable electrons to tunnel through the tunnel barrier between the interfacial reference layer and the free layer. A first in-situ alignment is provided between a tunnel barrier lattice structure of the tunnel barrier and an interfacial reference layer lattice structure of the interfacial reference layer. A second in-situ alignment is provided between the tunnel barrier lattice structure of the tunnel barrier and a free layer lattice structure of the free layer. The PMA reference layer lattice structure is not aligned with the interfacial reference layer lattice structure.

A method for fabricating an electronic device including a semiconductor memory includes: forming a memory layer over a substrate; forming a memory element by selectively etching the memory layer, wherein forming the memory element includes forming an etching residue on a sidewall of the memory element, the etching residue including a first metal; and forming a spacer by implanting oxygen and a second metal into the etching residue, the spacer including a compound of the first metal-oxygen-the second metal, the second metal being different from the first metal.

A magnetic memory device includes a memory cell array comprising memory cells including magnetic tunnel junction elements. Each memory cell is electrically connected between a source line and a bit line. A control circuit is configured to perform a screening test on the memory cell array before writing data to the memory cell array. The screening test determines whether an abnormal cell is present in the memory cell array. The controller applies a first writing voltage to the write data to the memory cell array if the abnormal cell is not present, or applies a second writing voltage to write data to the memory cell array if the abnormal cell is present. The second writing voltage is different from the first writing voltage.

A storage element includes a storage layer having a magnetization perpendicular to a layer surface and storing information according to a magnetization state of a magnetic material; a fixed magnetization layer having the magnetization as a reference of the information of the storage layer and perpendicular to the layer surface; an interlayer formed of a nonmagnetic material and interposed between the storage layer and the fixed magnetization layer; a coercive force enhancement layer adjacent to the storage layer, opposite to the interlayer, and formed of Cr, Ru, W, Si, or Mn; and a spin barrier layer formed of an oxide, adjacent to the coercive force enhancement layer, and opposite to the storage layer. The storage layer magnetization is reversed using spin torque magnetization reversal caused by a current in a lamination direction of a layer structure including the storage layer, the interlayer, and the fixed magnetization layer, thereby storing information.

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a substrate; a plurality of variable resistance elements formed over the substrate and arranged as a matrix, spacer patterns formed over the substrate to surround the variable resistance elements in the matrix with a thickness sufficient to define contact holes between the variable resistance elements, and a source line contact buried in the contact hole.

A magnetic memory includes a deformable base plate, a spin device element coupled with the deformable base plate and storing a data as a magnetization direction, and a bending mechanism to bend the deformable base plate. At least one of upper and lower surfaces of the deformable base plate faces a space which is not filled with solid substance.

An electronic device may be provided to include: first and second active regions arranged adjacent to each other in a second direction; a gate structure extended in the second direction; a first source region and a first drain region formed in the first active region; a second source region and a second drain region formed in the second active region; a source line contact formed over the first and second source regions and connected to the first and second source regions; a source line connected to the source line contact over the source line contact and extended in a first direction; first and second stacked structures formed over the first and second drain regions; and first and second bit lines formed over the first and second stacked structures, wherein the first and second bit lines are extended in the first direction.

A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a N.sub.2O:silane flow rate ratio of at least 1:1 but less than 15:1. A N.sub.2O plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.