Array Substrate And Method of Manufacturing the Same, And Display Apparatus

Abstract

The present disclosure provides an array substrate and a method of manufacturing the same and a display apparatus in which the array substrate is applied. In one embodiment, the method of manufacturing an array substrate at least includes the steps of: forming a first electrode layer, a metal gate layer and a first layer of non-oxide insulation material, the first layer of non-oxide insulation material being formed on an upper surface of the metal gate layer; forming, by using one patterning process, a pattern including a first electrode and a gate such that, after completion of the patterning process, a first non-oxide insulation layer is further formed on the gate and a first sub-electrode belonging to the first electrode layer is further formed below the gate. This method of manufacturing the array substrate is simple, which facilitates mass production of the array substrate as well as the display apparatus.

Claims

1. A method of manufacturing an array substrate, the method comprising steps of: forming a first electrode layer, a metal gate layer and a first layer of non-oxide insulation material, the first layer of non-oxide insulation material being formed on an upper surface of the metal gate layer; and forming, by using one patterning process, a pattern including a first electrode and a gate such that, after completion of the patterning process, a first non-oxide insulation layer is further formed on the gate and a first sub-electrode belonging to the first electrode layer is further formed below the gate.

2. The method of according to claim 1, after the step of forming the first electrode layer, further comprising steps of: forming a semiconductor layer; and further forming a pattern including an active layer, while forming the pattern including the first electrode and the gate by using one patterning process.

3. The method according to claim 2, after the step of forming the pattern including the first electrode, the gate and the active layer by using one patterning process, further comprising steps of: forming a third insulation layer, and, forming, by using one patterning process, a pattern including a via hole, the via hole being formed at a region that corresponds to the active layer and being served as a channel for an electrical connection between source and drain electrodes and the active layer; and forming successively a second electrode layer and a metal source-drain layer on the third insulation layer, and, forming, by using one patterning process, patterns including a source electrode, a drain electrode and a second electrode such that, after completion of the patterning process, a second sub-electrode positioned below the source and drain electrodes and belonging to the second electrode layer is formed at a position where the via hole is, and the source and drain electrodes are electrically connected to the active layer via the second sub-electrode.

4. The method of according to claim 1, after the step of forming the first electrode layer, further comprising steps of: forming a semiconductor layer, a metal source-drain layer and a second layer of non-oxide insulation material, the second layer of non-oxide insulation material being formed on an upper surface of the metal source-drain layer; an further forming a pattern including an active layer, a source electrode and a drain electrode, while forming the pattern including the first electrode and the gate by using one patterning process, such that, after completion of the patterning process, a second non-oxide insulation layer is formed on both the source electrode and the drain electrode.

5. The method according to claim 4, after the step of forming the pattern including the first electrode, the gate, the active layer, the source electrode and the drain electrode by using one patterning process, further comprising steps of: forming a third insulation layer, and, forming, by using one patterning process, a pattern including a via hole, the via hole being formed at a region that corresponds to the drain electrode, passing through the third insulation layer and the second non-oxide insulation layer, and being served as a channel for an electrical connection between the drain electrode and a second electrode; forming a second electrode layer on the third insulation layer, and, forming, by using one patterning process, a pattern including the second electrode.

6. The method of manufacturing an array substrate according to claim 1, after the step of forming the pattern including the first electrode and the gate by using one patterning process, further comprising steps of: forming a third insulation layer, forming successively a semiconductor layer and a metal source-drain layer on the third insulation layer, and correspondingly, forming, by using one patterning process, a pattern including an active layer, a source electrode and a drain electrode; and forming the second electrode layer, and correspondingly, forming, by using one patterning process, a pattern including the second electrode.

7. The method according to claim 1, wherein a material for the metal gate layer and the metal source-drain layer includes copper or copper alloy.

8. The method of according to claim 3, wherein a material for the first layer of non-oxide insulation material and the second layer of non-oxide insulation material includes silicon nitride or aluminum nitride.

9. The method according to claim 1, after the step of forming the first electrode, further comprising a step of implementing an annealing process for the first electrode.

10. The method according to claim 3, wherein, the second electrode comprises a slit electrode.

11. An array substrate which is manufactured by the method of according to claim 1.

12. A display apparatus, which comprises an array substrate according to claim 11.

13. The method according to claim 5, wherein, the second electrode comprises a slit electrode.

14. The method according to claim 6, wherein, the second electrode comprises a slit electrode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1a is a state diagram in which a step of forming, by using one patterning process, a pattern including a first electrode and a gate, of a method of manufacturing an array substrate according to a first embodiment of the present disclosure, has been implemented;

[0011] FIG. 1b is a state diagram in which a step of forming correspondingly, by using one patterning process, a pattern including an active layer, a source electrode and a drain electrode, of the method of manufacturing the array substrate according to the first embodiment of the present disclosure, has been implemented;

[0012] FIG. 1c is a state diagram in which a step of forming correspondingly, by using one patterning process, a pattern including a second electrode, of the method of manufacturing the array substrate according to the first embodiment of the present disclosure, has been implemented;

[0013] FIG. 2a is a state diagram in which a step of forming, by using one patterning process, a pattern including a first electrode, a gate and an active layer, of a method of manufacturing an array substrate according to a second embodiment of the present disclosure, has been implemented;

[0014] FIG. 2b is a state diagram in which a step of forming, by using one patterning process, a pattern including a via hole, of the method of manufacturing the array substrate according to the second embodiment of the present disclosure, has been implemented;

[0015] FIG. 2c is a state diagram in which a step of forming simultaneously, by using one patterning process, patterns including a source electrode and a drain electrode and including a second electrode, of the method of manufacturing the array substrate according to the second embodiment of the present disclosure, has been implemented;

[0016] FIG. 2d is another state diagram in which a step of forming simultaneously, by using one patterning process, patterns including a source electrode and a drain electrode and including a second electrode, of the method of manufacturing the array substrate according to the second embodiment of the present disclosure, has been implemented;

[0017] FIG. 3a is a state diagram in which a step of forming, by using one patterning process, a pattern including a first electrode, a gate, an active layer, a source electrode and a drain electrode, of a method of manufacturing an array substrate according to a third embodiment of the present disclosure, has been implemented;

[0018] FIG. 3b is a state diagram in which a step of forming, by using one patterning process, a pattern including a via hole, of the method of manufacturing the array substrate according to the third embodiment of the present disclosure, has been implemented; and

[0019] FIG. 3c is a state diagram in which a step of forming, by using one patterning process, a pattern including a second electrode, of the method of manufacturing the array substrate according to the third embodiment of the present disclosure, has been implemented.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] In order to provide a more clear understanding of technique solutions of the present disclosure, an array substrate and a method of manufacturing the same, and a display apparatus of the present disclosure will be further described hereinafter in detail and completely with reference to the attached drawings.

[0021] According to a first embodiment of the present disclosure, a method of manufacturing an array substrate at least comprises the following steps of:

[0022] forming a first electrode layer, a metal gate layer and a first layer of non-oxide insulation material, the first layer of non-oxide insulation material being formed on an upper surface of the metal gate layer.

[0023] A pattern including a first electrode 1 and a gate 2 is formed by using one patterning process such that, after completion of the patterning process, a first non-oxide insulation layer 3 is formed on an upper surface of the gate 2 and a first sub-electrode 4 belonging to the first electrode layer is further formed below the gate 2. That is to say, the first electrode layer, after the patterning process, is formed with the pattern including the first sub-electrode 4 and the first electrode 1, as shown in FIG. 1a.

[0024] Specifically, material for the first layer of non-oxide insulation material includes silicon nitride or aluminum nitride; and, material for the metal gate layer and metal source-drain layer includes copper. Due to its relatively high electrical conductivity, as a result, it can facilitate conductions of data signal and scanning signal.

[0025] It can be understood that, the method of manufacturing an array substrate according to this embodiment, with the help of the first non-oxide insulation layer 3 formed on the upper surface of the gate 2 that is of oxidizable and conductive material such as copper and the like, prevents a surface of the gate 2 from being oxidized when a subsequent process (e.g., an annealing process for the first electrode 1) is implemented. Hence, by virtue of forming the pattern not only including the first electrode 1 but also including the gate 2 by using one patterning process, one time of patterning process can be at least reduced, which can simplify the process steps and thereby can improve the yield and economic efficiency.

[0026] Specifically, in this embodiment, after the forming, by using one patterning process, the pattern including the first electrode 1 and the gate 2, the method further comprises the following steps of:

[0027] forming a third insulation layer 5, forming successively a semiconductor layer and a metal source-drain layer on the third insulation layer 5, and correspondingly, forming, by using one patterning process, a pattern including an active layer 6, a source electrode 71 and a drain electrode 72, as shown in FIG. 1b.

[0028] The method further comprises forming a second electrode layer, and correspondingly, forming, by using one patterning process, a pattern including a second electrode 8. The second electrode 8 is a slit electrode, as shown in FIG. 1c.

[0029] And, preferably, after the forming the first electrode 1, the method further comprises, implementing an annealing process for the first electrode 1, so that resistance of the first electrode 1 is reduced, which facilitates uniform distribution of a voltage applied on the first electrode 1.

[0030] It should be mentioned that, the abovementioned method of manufacturing an array substrate should further comprise a process of forming a via hole for a connection between a scanning line and the gate line 2. Specifically, it not only can be formed at the same time as any one of the abovementioned patterning processes, but also can be formed separately by using one patterning process.

[0031] It should be noted that, in this embodiment, the first electrode 1 and the second electrode 8 can respectively be one and the other of a common electrode and a pixel electrode.

[0032] In a second embodiment of the present disclosure, there provides a method of manufacturing an array substrate, which is similar to that of the abovementioned first embodiment. The description is omitted for clarity, excepting the following differences between the two. Specifically, in this embodiment, after the forming the first electrode layer, the method further comprises: forming a semiconductor layer; and, further forming a pattern including an active layer 6, while forming the pattern including the first electrode 1 and the gate 2 by using one patterning process.

[0033] From the above, in the method of manufacturing an array substrate according to this embodiment, the pattern including not only the first electrode 1 but also the gate 2 and the active layer 6 can be formed by using one patterning process, as shown in FIG. 2a. This can also reduce at least one time of patterning process, which can simplify the process steps and thereby can improve the yield and economic efficiency.

[0034] Preferably, an ohmic contact material layer is further formed on the semiconductor layer. After the pattern including the first electrode 1, the gate 2 and the active layer 6 is formed by using one patterning process, an ohmic contact layer 9 is formed on the active layer 6, as shown in FIG. 2a, for achieving an ohmic contact between source and drain electrodes 7 and the active layer 6 that is of material such as amorphous silicon, polysilicon, monocrystalline silicon and the like. If the active layer 6 is an oxide semiconductor, an electrical connection between the active layer 6 and the source 71 and drain 72 electrodes is an ohmic contact, here, no ohmic contact layer 9 is required.

[0035] Preferably, after the forming the pattern including the first electrode, the gate and the active layer by using one patterning process, the method further comprises steps of: forming a third insulation layer 5, and, forming, by using one patterning process, a pattern including a via hole 51, the via hole 51 being formed at a region that corresponds to the active layer 6 and being served as a channel for an electrical connection between the source and drain electrodes 7 and the active layer 6, as shown in FIG. 2b.

[0036] The method further comprises forming successively a second electrode layer and a metal source-drain layer on the third insulation layer 5, and, forming, by using one patterning process, patterns including a source electrode 71, a drain electrode 72 and a second electrode 8 such that, after completion of the patterning process, a second sub-electrode 10 positioned below the source and drain electrodes 7 and belonging to the second electrode layer is formed at a position where the via hole 51 is, and the source and drain electrodes 7 are electrically connected to the active layer 6 via the second sub-electrode 10, as shown in FIG. 2c.

[0037] It can be understood that, the patterns including the source electrode 71, the drain electrode 72 and the second electrode 8 are formed simultaneously by using one patterning process, which further simplifies manufacturing process of the array substrate.

[0038] Similarly, the abovementioned method of manufacturing an array substrate should further comprise a process of forming a via hole for a connection between a scanning line and the gate 2. Specifically, it not only can be formed at the same time as any one of the abovementioned patterning processes, but also can be formed separately by using one patterning process. In this embodiment, preferably, the via hole for a connection between a scanning line and the gate 2 is formed while forming a pattern including a via hole 51 in the third insulation layer 5 by using one patterning process.

[0039] It should be noted that, in this embodiment of FIG. 2b, only one via hole 51 is disposed at a region, that corresponds to the active layer 6, of the third insulation layer 5, which makes structure of the array substrate simple. However, in practical applications, referring to FIG. 2d, via holes 51, which corresponds respectively to the source electrode 71 and the drain electrode 72, can also be disposed at a region, that corresponds to the active layer 6, of the third insulation layer 5, which not only helps on an isolation between the source electrode 71 and the drain electrode 72, but also protects the channels from being etched.

[0040] According to a third embodiment of the present disclosure, there provides a method of manufacturing an array substrate, which is similar to those of the abovementioned embodiments. The description is omitted for clarity, excepting the following differences among the three. Specifically, in this embodiment, after the forming the first electrode layer, the method further comprises: forming a metal source-drain layer and a second layer of non-oxide insulation material, the second layer of non-oxide insulation material being formed on an upper surface of the metal source-drain layer. A pattern including an active layer 6, a source electrode 71 and a drain electrode 72 is further formed while forming the pattern including the first electrode 1 and the gate 2 by using one patterning process, such that, after completion of the patterning process, a second non-oxide insulation layer 11 is formed on both the source electrode 71 and the drain electrode 72. It can be understood that, with the help of the second non-oxide insulation layer 11, the source electrode 71 and the drain electrode 72, which are of oxidizable and conductive material such as copper and the like, are prevented from being oxidized during a subsequent process (e.g., an annealing process for the first electrode 1).

[0041] From the above, the method of manufacturing an array substrate according to this embodiment, by virtue of forming the pattern including not only the first electrode 1 but also the gate 2, the active layer 6, the source electrode 71 and the drain electrode 72 by using one patterning process, as shown in FIG. 3a, can also reduce at least one time of patterning process, which can simplify the process steps and thereby can improve the yield and economic efficiency.

[0042] After the forming the pattern including the first electrode, the gate, the active layer, the source electrode and the drain electrode by using one patterning process, the method further comprises steps of:

[0043] forming a third insulation layer 5, and, forming, by using one patterning process, a pattern including a via hole 51, the via hole 51 being formed at a region that corresponds to the drain electrode 72, passing through the third insulation layer 5 and the second non-oxide insulation layer 11, and being served as a channel for an electrical connection between the drain electrode 72 and the second electrode 8, as shown in FIG. 3b.

[0044] The method further comprises forming a second electrode layer on the third insulation layer 5, and, forming, by using one patterning process, a pattern including the second electrode 8, as shown in FIG. 3c.

[0045] An array substrate is provided according to an embodiment of the present disclosure. The array substrate is manufactured by the method of manufacturing an array substrate according to any one of the abovementioned first to third embodiments.

[0046] The array substrate according to the embodiment of the present disclosure is manufactured by the method of manufacturing an array substrate according to any one of the abovementioned first to third embodiments of the present disclosure. Hence, the manufacturing process is simple, which facilitates mass production of the array substrate and improves economic efficiency.

[0047] A display apparatus is further provided according to an embodiment of the present disclosure. The display apparatus comprises an array substrate according to the abovementioned embodiment.

[0048] The display apparatus according to the embodiment of the present disclosure adopts an array substrate according to the abovementioned embodiment. The manufacturing process of the array substrate is simple, which facilitates mass production of the array substrate and thereby achieves mass production of the display apparatus and improves economic efficiency.

[0049] It should be understood that, the abovementioned embodiments are exemplary ones merely used to illustrate principles of the present invention, but not to limit the present invention. It should be understood by those skilled in the art that, all of changes and modifications, made within principles and spirit of the present invention, should be included within the scope of the present invention.