Disclosed herein are a thin-film transistor and a preparation method therefor, and a memory and a display. The thin-film transistor comprises a first source/drain layer (1); a second source/drain layer (3); an insulating layer (2), which is located between the first source/drain layer (1) and the second source/drain layer (3); a channel layer (4), which is embedded in the first source/drain layer (1) and the insulating layer (2); and a gate electrode (5), which is embedded in the channel layer (4), wherein an embedded end of the channel layer (4) is in contact with the second source/drain layer (3), and a top end of the channel layer (4) and a top end of the gate electrode (5) are both flush with the first source/drain layer (1). The thin-film transistor provided in the present disclosure is a CAA architecture in which an annular channel is arranged surrounding the gate electrode (5), such that the performance of the transistor can be improved, and the power consumption can be reduced; moreover, there is no gate electrode (5) in the horizontal direction covering the first source/drain layer (1), such that the parasitic capacitance and current leakage of the gate electrode can be reduced.

An IC structure includes a first transistor, first gate spacers, a second transistor, second gate spacers, a backside metal line, and a metal contact. The first transistor includes first source/drain regions and a first gate structure between the first source/drain regions. The first gate spacers space apart the first source/drain regions from the first gate structure. The second transistor comprises second source/drain regions and a second gate structure between the second source/drain regions. The second gate spacers space apart the second source/drain regions from the second gate structure. The first gate spacers and the second gate spacers extend along a first direction. The backside metal line extends between the first transistor and the second transistor along a second direction. The first metal contact wraps around one of the second source/drain regions and has a protrusion interfacing the backside metal line.

A semiconductor device includes: an oxide semiconductor layer having a pattern; a gate electrode facing the oxide semiconductor layer; a gate insulating layer provided between the oxide semiconductor layer and the gate electrode; a first insulating layer provided above the gate electrode and having a first opening overlapping a pattern edge portion of the oxide semiconductor layer in a plan view; and a first electrode provided above the first insulating layer and inside the first opening, and contacting the oxide semiconductor layer so as to cover the pattern edge portion of the oxide semiconductor layer in a bottom part of the first opening.

Disclosed transistor structures include a gate electrode, an active layer, a gate dielectric layer separating the active layer from the gate electrode, a source electrode, a drain electrode, and a hydrogen-rich material layer separating the source electrode and the drain electrode from the active layer. The presence of hydrogen in the hydrogen-rich material layer may act to reduce contact resistances and Schottky barriers between the source electrode and the active layer, and between the drain electrode and the active layer, thus leading to improved device performance. The disclosed transistor structures may be formed in a BEOL process and may be incorporated with other BEOL circuit components. As such, the disclosed transistor structures may include materials that may be processed at low temperatures and thus, may not damage previously fabricated devices.

A method includes forming a gate stack, growing a source/drain region on a side of the gate stack through epitaxy, depositing a contact etch stop layer (CESL) over the source/drain region, depositing an inter-layer dielectric over the CESL, etching the inter-layer dielectric and the CESL to form a contact opening, and etching the source/drain region so that the contact opening extends into the source/drain region. The method further includes depositing a metal layer extending into the contact opening. Horizontal portions, vertical portions, and corner portions of the metal layer have a substantially uniform thickness. An annealing process is performed to react the metal layer with the source/drain region to form a source/drain silicide region. The contact opening is filled to form a source/drain contact plug.

A semiconductor device includes a substrate; gate electrodes spaced apart from each other and stacked in a direction, perpendicular to an upper surface of the substrate; first and second horizontal conductive layers sequentially stacked between the substrate and the gate electrodes; and a channel structure passing through the gate electrodes and extending perpendicularly, and including a channel layer contacting the first horizontal conductive layer, wherein the channel layer has a region having a reduced diameter below a first level in which a lower surface of a lowermost gate electrode is located, among the gate electrodes, and the channel structure further includes a metal silicide region located below the first level and in the channel structure to contact the channel layer.

A display module and a method for manufacturing the same are provided. The display module manufacturing method includes: forming a semiconductor pattern on a substrate; forming a first insulating layer covering the semiconductor pattern on the substrate; forming a gate electrode on a region of the first insulating layer corresponding to a gate region of the semiconductor pattern; forming a second insulating layer covering the gate electrode on the first insulating layer; forming a first hole passing through the first insulating layer and the second insulating layer to expose a drain region of the semiconductor pattern and forming a second hole passing through the first insulating layer and the second insulating layer to expose a source region of the semiconductor pattern; and forming a first barrier pattern on the drain region in the first hole and a second barrier pattern on the source region in the second hole, and forming a drain electrode on the first barrier pattern and a source electrode on the second barrier pattern.

A display device includes a substrate, a buffer layer disposed on the substrate, and a pixel circuit layer disposed on the buffer layer. The pixel circuit layer includes an active pattern disposed on the buffer layer, a gate-insulating layer disposed on the active pattern, a gate electrode overlapping a channel area of the active pattern, a first electrode connected to a first doped area of the active pattern, a second electrode connected to a second doped area of the active pattern, a passivation layer covering the gate electrode, and the first and second electrodes, and a first metal layer disposed under the first and second electrodes, and the gate electrode.

A method of fabricating a pixel array substrate includes forming a semiconductor layer on a substrate, forming a metal layer stack on the semiconductor layer, forming a photoresist pattern on the metal layer stack, and removing part of the metal layer stack and the semiconductor layer not covered by the photoresist pattern at one time using a dry etching process to form a source, a drain, and a semiconductor pattern of an active device. The metal layer stack includes a first titanium layer, an aluminum layer, and a second titanium layer. The semiconductor pattern has a groove located between the source and the drain. The source and the drain respectively have a source edge and a drain edge opposite to each other, which defines two opposite side walls of the groove respectively. A pixel array substrate produced by using the method of fabricating the pixel array substrate is also disclosed.

A semiconductor device includes a semiconductor layer including a trench, wherein the trench is adjacent a mesa, a first metal silicide layer on a top portion of the mesa, and a second metal silicide layer on a bottom portion of the trench. The first metal silicide layer has a thickness that is no more than about 1 to 1.5 times greater than a thickness of the second metal silicide layer. Related methods of forming a semiconductor device are disclosed.