An oxide semiconductor device includes a first insulation layer pattern and a second insulation layer pattern disposed on a substrate, an active layer disposed on the first and second insulation layer patterns, the active layer including a source region including the first insulation layer pattern, a drain region including the second insulation layer pattern, and a channel region disposed between the source and drain regions, a source electrode contacting the source region, and a drain electrode contacting the drain region.

The present disclosure provides a metal oxide thin film transistor, wherein an oxygen deficiency adsorptive removal layer comprising an oxygen deficiency adsorptive removal material is provided between an active layer and a source, and/or between the active layer and a drain. The standard Gibbs free energy of formation of an oxide of the oxygen deficiency adsorptive removal material in a unit volume is larger than that of a metal oxide in the active layer. The present disclosure further provides a display substrate comprising the metal oxide thin film transistor and a display device comprising the display substrate.

An organic EL element including: a TFT substrate having a TAOS-TFT; and an organic EL unit having a lower electrode. The lower electrode includes an aluminum containing metal layer, a transition metal containing oxide layer disposed between the aluminum containing metal layer and the TFT substrate, and an aluminum containing oxide layer disposed between the aluminum containing metal layer and the transition metal containing oxide layer and in contact with both the aluminum containing metal layer and the transition metal containing oxide layer. The aluminum containing oxide layer contains aluminum oxide. The transition metal containing oxide layer contains tungsten oxide and has a density of 6.5 g/cm.sup.3 or more.

A thin film transistor substrate includes a semiconductor channel layer made of an oxide semiconductor, protective insulating layers that cover the semiconductor channel layer, a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode. The second source electrode is located on the first source electrode and connected with the semiconductor channel layer through a first contact hole. The second drain electrode is located on the first drain electrode and connected with the semiconductor channel layer through a second contact hole.

A display may have an array of pixels that forms an active display area for displaying images. An inactive border area of the display may have contact pads to which integrated circuits and flexible printed circuits may be attached. The contact pads may be free of organic planarization layers and may be formed from multiple stacked conductive layers. The inactive portion of the display may include electrostatic discharge protection structures associated with the pads, metal layers that form signal paths extending between the pads and the pixels, interlayer dielectric layers for protecting the metal layers that form the signal paths, polysilicon footer structures that help prevent undercutting of gate insulator material in the vicinity of the pads, and other pad and signal line structures.

A highly reliable semiconductor device with stable electrical characteristics and a method for manufacturing the semiconductor device are provided. A separation layer is formed between a source electrode and a drain electrode. The separation layer is formed using a material having a high insulating property. The separation layer between the source electrode and the drain electrode can reduce a difference in level of each of the source electrode and the drain electrode, which can improve coverage with a layer formed over the source electrode and the drain electrode. The separation layer between the source electrode and the drain electrode can prevent an unintended electrical short circuit of the source electrode and the drain electrode. The separation layer can be formed by introducing oxygen to a conductive layer.

An array substrate, a display device and a method of producing the array substrate are provided, and the array substrate includes a substrate and a thin film field effect transistor and a data line formed on the substrate, and the thin film field effect transistor includes a gate electrode, an active layer, a source electrode and a drain electrode, a gate insulating layer is formed between the gate electrode and the active layer, and the array substrate includes: a protection layer formed between the gate insulating layer and the data line and being in direct contact with the data line; and the protection layer is provided on the same layer with and has the same material with the active layer.

As source and drain wiring, a base layer and a cap layer are each formed of a MoNiNb alloy film, and a low-resistance layer is formed of Cu. The resultant laminated metal film is patterned through one-time wet etching to form a drain electrode and a source electrode. Cu serving as a main wiring layer does not corrode because of being covered with a MoNiNb alloy having good corrosion resistance. Further, even when a protective insulating film including an oxide is formed by plasma CVD in an oxidizing atmosphere, Cu is not oxidized. With the wet etching, the sidewall taper angle of the laminated metal film can be controlled to 20 degrees or more and less than 70 degrees.

A method of making a nanowire device incudes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.

A method of making a nanowire device includes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.