A novel semiconductor device is provided. The semiconductor device combines a lateral-channel transistor and a vertical-channel transistor. The lateral-channel transistor is employed as a p-channel transistor and the vertical-channel transistor is employed as an n-channel transistor to achieve a CMOS semiconductor device. An opening is provided in the insulating layer in a region overlapping with a gate electrode of the lateral-channel transistor, and the vertical-channel transistor is formed in the opening. An oxide semiconductor is used for a semiconductor layer of the vertical-channel transistor.

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and a bottom isolation feature formed over the substrate. The semiconductor structure also includes a bottom semiconductor layer formed over the bottom isolation feature and nanostructures formed over the bottom semiconductor layer. The semiconductor structure also includes a source/drain structure attached to the nanostructures and covering a portion of the bottom isolation feature.

To reduce power consumption and suppress display degradation of a liquid crystal display device. To suppress display degradation due to an external factor such as temperature. A transistor whose channel formation region is formed using an oxide semiconductor layer is used for a transistor provided in each pixel. Note that with the use of a high-purity oxide semiconductor layer, off-state current of the transistor at a room temperature can be 10 aA/m or less and off-state current at 85 C. can be 100 aA/m or less. Consequently, power consumption of a liquid crystal display device can be reduced and display degradation can be suppressed. Further, as described above, off-state current of the transistor at a temperature as high as 85 C. can be 100 aA/m or less. Thus, display degradation of a liquid crystal display device due to an external factor such as temperature can be suppressed.

A semiconductor device includes a substrate. Semiconductor layers are stacked one above another over the substrate. A gate structure wraps around each of the semiconductor layers. Epitaxial layers are over the substrate and in contact with opposite ends of a bottommost one of the semiconductor layers. Source/drain epitaxial structures are over and in contact with the epitaxial layers, respectively. Dielectric structures vertically between the epitaxial layers and the respective source/drain epitaxial structures, respectively.

A thin film transistor, a memory, and a method of manufacturing a thin film transistor are provided, which relate to a field of semiconductor device technology. The thin film transistor includes a substrate; a gate on a surface of the substrate; an insulation layer covering the gate; a source and a drain; a channel between the insulation layer and the source and the drain, wherein the source and the drain are located on a surface of the channel away from the substrate; and an insulation dielectric layer between the source and the drain, wherein the insulation dielectric layer partially overlaps with the channel in a first direction, wherein the substrate, the gate, the insulation layer, the source and the drain, the channel, and the insulation dielectric layer are stacked in the first direction.

One aspect of the invention relates to a field effect transistor (3) comprising: a channel region (11); a source region (12) and a drain region (13); a gate structure (14) comprising: a gate dielectric layer (14b); a gate electrode (14a) with a first work function (W.sub.1); and a lateral gate conductor (14c) disposed at least against the flank of the gate electrode (14a) located on the side of the drain region (13), the lateral gate conductor (14c) extending to the gate dielectric layer (14b) in direct contact with the gate electrode (14a) and having a second work function (W.sub.2);
the second work function (W.sub.2) being: strictly greater than the first work function (W.sub.1) when the transistor is of type p; strictly lower than the first work function (W.sub.1) when the transistor is of type n.

Objects are to provide a display device the power consumption of which is reduced, to provide a self-luminous display device the power consumption of which is reduced and which is capable of long-term use in a dark place. A circuit is formed using a thin film transistor in which a highly-purified oxide semiconductor is used and a pixel can keep a certain state (a state in which a video signal has been written). As a result, even in the case of displaying a still image, stable operation is easily performed. In addition, an operation interval of a driver circuit can be extended, which results in a reduction in power consumption of a display device. Moreover, a light-storing material is used in a pixel portion of a self-luminous display device to store light, whereby the display device can be used in a dark place for a long time.

A number of MOSFET architectures provide high-voltage capability (both drain-source breakdown voltage BV.sub.DSS and ON-state breakdown voltage BV.sub.ON), low current leakage, and extended linearity. Embodiments of the invention overcome the limitations of conventional NEDMOS and LDMOS device designs by providing a low-resistance path for hole collection and by purposefully exhibiting multiple voltage thresholds V.sub.TH in different segments of the device. Embodiments includes NEDMOS and LDMOS device designs having multiple body contact regions for improved hole collection, sub-gate doped stripes or segments for even better hole collection and linearity, and sub-gate doped edge regions for increased local V.sub.TH and thus decreased current leakage. P hole-collection stripes and P+ body contact regions may be formed of a semiconductor material that includes germanium. The inventive MOSFETs may be arranged as multi-MOSFET array elements, and multiple array elements may be arranged in a larger array.

A method includes following steps. A semiconductor fin is formed on a substrate. A source/drain recess is formed in the semiconductor fin. A first isolation sidewall dielectric and a second isolation sidewall dielectric are formed lining opposite sidewalls of the source/drain recess. An epitaxial layer is formed in the source/drain recess. The epitaxial layer is recessed such that a top surface of the epitaxial layer is lower than top surfaces of the first and second isolation sidewall dielectrics. An epitaxial source/drain region is formed on the recessed epitaxial layer. A gate structure is formed adjacent the epitaxial source/drain region.

Disclosed is a display device including a transistor showing extremely low off current. In order to reduce the off current, a semiconductor material whose band gap is greater than that of a silicon semiconductor is used for forming a transistor, and the concentration of an impurity which serves as a carrier donor of the semiconductor material is reduced. Specifically, an oxide semiconductor whose band gap is greater than or equal to 2 eV, preferably greater than or equal to 2.5 eV, more preferably greater than or equal to 3 eV is used for a semiconductor layer of a transistor, and the concentration of an impurity which serves as a carrier donor included is reduced. Consequently, the off current of the transistor per micrometer in channel width can be reduced to lower than 10 zA/m at room temperature and lower than 100 zA/m at 85 C.