Si pillars 22a to 22d stand on an N.sup.+ layer 21 connected to a source line SL. Lower portions of the Si pillars 22a to 22d are surrounded by a HfO.sub.2 layer 25a, which is surrounded by TiN layers 26a and 26b that are respectively connected to plate lines PL1 and PL2 and are isolated from each other. Upper portions of the Si pillars 22a to 22d are surrounded by a HfO.sub.2 layer 25b, which is surrounded by TiN layers 28a and 28b that are respectively connected to word lines WL1 and WL2 and are isolated from each other. A thickness Lg1 of the TiN layer 26a on a line X-X′ is smaller than twice a thickness Lg2 of the TiN layer 26a on a line Y-Y′ and is larger than or equal to the thickness Lg2. The thickness Lg1 of the TiN layer 28a on the line X-X′ is smaller than twice the thickness Lg2 of the TiN layer 28a on the line Y-Y′.

A memory apparatus includes pages each including a plurality of memory cells arranged in a column on a substrate. A voltage applied to each of a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell included in each page is controlled to perform a page write operation for retaining holes, which have been formed through an impact ionization phenomenon or using a gate induced drain leakage current, in a channel semiconductor layer, or a voltage applied to each of the first gate conductor layer, the second gate conductor layer, a third gate conductor layer, a fourth gate conductor layer, the first impurity layer, and the second impurity layer is controlled to perform a page erase operation for removing the holes from the channel semiconductor layer. The first impurity layer in the memory cell connects to a source line. The second impurity layer connects to a bit line. One of the first gate conductor layer and the second gate conductor layer connects to a word line, and the other connects to a first drive control line. The bit line connects to a sense amplifier circuit via a switch circuit. During a page read operation, page data in a group of memory cells selected by the word line is read by the sense amplifier circuit. During each of the page write operation, the page erase operation, and the page read operation, an identical fixed voltage is applied to the first drive control line.

Provided is a memory device including a substrate, a plurality of bit-line structures, a plurality of bit-line contacts, and a plurality of protective structures. The substrate has a plurality of active areas. The plurality of bit-line structures are disposed on the substrate in parallel along a X direction. The plurality of bit-line contacts are respectively disposed at overlaps of the plurality of bit-line structures and the plurality of active areas, and electrically connect the plurality of bit-line structures and the plurality of active areas. The plurality of protective structures are disposed at least on a first sidewall and a second sidewall of the plurality of bit-line contacts. A method of forming a memory device is also provided.

The present disclosure relates to a semiconductor device and a fabricating method thereof, the semiconductor device includes a substrate, a plurality of gate structures, a plurality of isolation fins, and at least one bit line. The gate structures are disposed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. The isolation fins are disposed on the substrate, with each of the isolation fins being parallel with each other and extending along the first direction, over each of the gate structures respectively. The at least one bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The at least one bit line comprises a plurality of pins extending toward the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.

The present invention provides an active region structure, the active region structure includes a plurality of sub-closed conductive patterns located on a substrate, the sub-closed conductive patterns are in contact with each other and form a larger closed pattern, a first boundary of the larger closed pattern extends along a horizontal direction, and a second boundary of the larger closed pattern extends along a vertical direction.

The invention provides a semiconductor storage device including a substrate, a plurality of active areas which are arranged along an oblique direction, a dummy active area pattern, and the dummy active area pattern comprises a first edge principal axis pattern and a plurality of first long branches and a plurality of short branches connecting edge principal axis patterns, and a plurality of storage nodes are in contact with each other. According to the invention, a part of the storage node contacts are arranged on the dummy active area pattern, so that the difficulty of the manufacturing process can be reduced, and the surrounding storage node contacts can serve as protection structures to protect components and prevent the components from being physically or electrically affected.

Methods of forming memory devices are described. A molybdenum silicide nucleation layer is formed, and the substrate is soaked in a titanium precursor prior to a bulk molybdenum gap fill process. In other embodiments, a molybdenum silicide film is formed in a first process cycle and a second process cycle is performed where the substrate is exposed to a titanium precursor. In further embodiments, a substrate having at least one feature thereon is exposed to a first titanium precursor and a nitrogen-containing reactant. The substrate is then soaked in a second titanium precursor, and then is exposed to a first molybdenum precursor followed by exposure to a silane to form a molybdenum silicide layer on a surface of the substrate.

The semiconductor device includes a first conductor and a second conductor; a first insulator to a third insulator; and a first oxide to a third oxide. The first conductor is disposed to be exposed from a top surface of the first insulator. The first oxide is disposed over the first insulator and the first conductor. A first opening reaching the first conductor is provided in the first oxide. The second oxide is disposed over the first oxide. The second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region. The third oxide is disposed over the second oxide. The second insulator is disposed over the third oxide. The second conductor is disposed over the second insulator. The third insulator is disposed to cover the first region and the second region and to be in contact with the top surface of the first insulator.

A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a capacitor, an electrode, and an interlayer film. The transistor includes a semiconductor layer, a gate, a source, and a drain; the transistor and the capacitor are placed to be embedded in the interlayer film. Below the semiconductor layer, one of the source and the drain is in contact with the electrode. Above the semiconductor layer, the other of the source and the drain is in contact with one electrode of the capacitor.

The present disclosure provides a memory circuit, a memory device and an operating method of the memory device. The memory device includes a storage transistor, a variable capacitance device and a control transistor. The variable capacitance device is electrically connected to the gate of the storage transistor, and the control transistor is connected to the storage transistor in series.