A semiconductor device includes a wide-bandgap semiconductor substrate of a first conductivity type, a wide-bandgap semiconductor deposition layer of the first conductivity type, semiconductor regions of a second conductivity type, a wide-bandgap semiconductor layer of the second conductivity type, first regions of the first conductivity type, and second regions of the first conductivity type. The width w of a plating film formed on a source electrode of the semiconductor device is greater than or equal to 10 m. Beneath the plating film, the wide-bandgap semiconductor layer is formed on the surface of one of the semiconductor regions of the second conductivity type.

According to the present invention, a semiconductor device includes a first conductivity type SiC layer, an electrode that is selectively formed upon the SiC layer, and an insulator that is formed upon the SiC layer and that extends to a timing region that is set at an end part of the SiC layer. The insulator includes an electrode lower insulating film that is arranged below the electrode, and an organic insulating layer that is arranged so as to cover the electrode lower insulating film. The length (A) of the interval wherein the organic insulating layer contacts the SiC layer is 40 m or more, and the lateral direction distance (B) along the electrode lower insulating layer between the electrode and SiC layer is 40 m or more.

A power semiconductor device is comprised of a plurality of zones having similar structure. Each of the zones may be characterized by a switching loss during transitions to a non-conducting state. The device is configured such that the switching loss is different between at least two of the zones. Further, the device is configured such that zones having greater switching losses transition to the non-conducting state before zones having lesser switching losses.

A semiconductor apparatus includes a semiconductor substrate, a semiconductor element, an edge termination region that surrounds the semiconductor element, a protective diode that has a first terminal and a second terminal, where the first terminal is positioned within the edge termination region and the second terminal is positioned outside the edge termination region, and a diffusion layer that has a floating potential, where the diffusion layer is provided in a gap portion between a region of the edge termination region that is aligned with the protective diode and the protective diode.

An embodiment of a structure for a high voltage device of the type which comprises at least a semiconductor substrate being covered by an epitaxial layer of a first type of conductivity, wherein a plurality of column structures are realized, which column structures comprises high aspect ratio deep trenches, said epitaxial layer being in turn covered by an active surface area wherein said high voltage device is realized, each of the column structures comprising at least an external portion being in turn realized by a silicon epitaxial layer of a second type of conductivity, opposed than said first type of conductivity and having a dopant charge which counterbalances the dopant charge being in said epitaxial layer outside said column structures, as well as a dielectric filling portion which is realized inside said external portion in order to completely fill said deep trench.

There is provided a power semiconductor device including: a first semiconductor region of a first conductivity type; second semiconductor regions formed in the first semiconductor region and being of a second conductivity type; a well region formed above the second semiconductor regions and being of the second conductivity type; and a source region formed in the well region and being of the first conductivity type, wherein the second semiconductor regions include 1 to n layers formed from a lower portion of the device extending a in a direction of height of the device, and in the case that the widest width of the of the second semiconductor region of the n.sup.th layer is P.sub.n, P.sub.1<P.sub.n (n2).

A method for manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is prepared. A first heating step of heating the silicon carbide substrate in an atmosphere of oxygen is performed. A second heating step of heating the silicon carbide substrate to a temperature of 1300 C. or more and 1500 C. or less in an atmosphere of gas containing nitrogen atoms or phosphorus atoms is performed after the first heating step. A third heating step of heating the silicon carbide substrate in an atmosphere of a first inert gas is performed after the second heating step. Thus, the silicon carbide semiconductor device in which threshold voltage variation is small, and a method for manufacturing the same can be provided.

In an active region, p.sup.+ regions are selectively disposed in a surface layer of an n.sup. drift layer on an n.sup.+ semiconductor substrate. A p-base layer is disposed on surfaces of the n.sup. drift layer and the P.sup.+ regions, and an MOS structure is disposed on the p-base layer. In another portion of the active region, a p.sup.+ region is disposed to be in contact with the source electrode on the p.sup.+ regions. In a breakdown voltage structure region (100), a JTE structure having at least a P.sup. region is disposed separately from the P.sup.+ regions and the p-base layer, to surround the active region. The P.sup. region is electrically in contact with the P.sup.+ region in a portion in which the MOS structure is not formed, in the vicinity of the boundary between the active region and the breakdown voltage structure region.

A semiconductor device according to an embodiment includes a SiC semiconductor layer, a gate electrode, a gate insulating film provided between the SiC semiconductor layer and the gate electrode, and a region that is provided between the SiC semiconductor layer and the gate insulating film and includes at least one element selected from the group consisting of antimony (Sb), scandium (Sc), yttrium (Y), lanthanum (La), and lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu). The concentration of the at least one element is equal to or greater than 110.sup.19 cm.sup.3 and equal to or less than 2.410.sup.22 cm.sup.3.

An insulated gate bipolar transistor (IGBT) manufacturing method comprises the following steps: providing a semiconductor substrate of a first conducting type, the semiconductor substrate having a first major surface and a second major surface (100); forming a field-stop layer of a second conducting type on the first major surface of the semiconductor substrate (200); growing an oxide layer on the field-stop layer (300); removing the oxide layer from the field-stop layer (400); forming an epitaxial layer on the field-stop layer from which the oxide layer has been removed; and then manufacturing an IGBT on the epitaxial layer (600). Before regular manufacturing of an IGBT, the surface defects of a substrate material are eliminated as many as possible before epitaxy is formed, and the quality of an epitaxial layer is improved, thereby improving the quality of the whole IGBT.