Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel material is between the gate and the source region. The first channel material is spaced from the gate by one or more insulative materials. Second channel material is between the first channel material and the source region, and directly contacts the source region. The first and second channel materials are transition metal chalcogenide. One of the source and drain regions is a hole reservoir region and the other is an electron reservoir region. Tunnel dielectric material may be between the first and second channel materials.

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a gate layer on the substrate; forming a first gate dielectric layer on the gate layer; forming a first channel layer on the first region and a second channel layer on the second region; and forming a first source/drain on the first channel layer and a second source/drain on the second channel layer.

Field-plate structures are disclosed for electrical field management in semiconductor devices. A field-plate semiconductor device comprises a semiconductor substrate, a first ohmic contact and a second ohmic contact disposed over the semiconductor substrate, one or more coupling capacitors, and one or more capacitively-coupled field plates disposed over the semiconductor substrate between the first ohmic contact and the second ohmic contact. Each of the capacitively-coupled field plates is capacitively coupled to the first ohmic contact through one of the coupling capacitors, the coupling capacitor having a first terminal electrically connected to the first ohmic contact and a second terminal electrically connected to the capacitively-coupled field plate.

A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.

A method of manufacturing a silicon carbide semiconductor device is provided. The method suppresses the increase in the number of manufacturing steps and is capable of suppressing the degradation of ohmic characteristics of an alloy layer with respect to a semiconductor substrate. The method includes a step of forming a metal layer made of a first metal on a semiconductor substrate made of silicon carbide; a step of forming a metal nitride film obtained by nitriding a second metal on the metal layer; a step of directing a laser light through the metal nitride film to form a layer of an alloy of silicon carbide in the semiconductor substrate and the first metal in the metal layer; and a step of forming an electrode on the metal nitride film.

The present invention provides a field effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first III-V compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first III-V compound layer, and source/drain electrodes are respectively located at each side of the gate electrode and on the first III-V compound layer. According to the present invention, the band width of the barrier layer is greater than that of the first III-V compound layer, and the band curvatures of the barrier layer and the first III-V compound layer are different, therefore, a two-dimensional electron gas (2DEG) is formed in the first III-V compound layer near the barrier layer boundary. Since the 2DEG has higher mobility, the performance of the filed effect transistor improved. Besides, the performance of the filed effect transistor also improved due to the structure is a gate-all-around structure.

Provided are electronic devices and methods of manufacturing same. An electronic device includes an energy barrier forming layer on a substrate, an upper channel material layer on the substrate, and a gate electrode that covers the upper channel material layer and the energy barrier forming layer. The gate electrode includes a side gate electrode portion that faces a side surface of the energy barrier forming layer. The side gate electrode may be configured to cause an electric field to be applied directly on the energy barrier forming layer via the side surface of the energy barrier forming layer, thereby enabling adjustment of the energy barrier between the energy barrier forming layer and the upper channel material layer. The electronic device may further include a lower channel material layer that is provided on the substrate and does not contact the upper channel material layer.

A semiconductor device includes a first semiconductor layer formed on a substrate; a second semiconductor layer and a third semiconductor layer formed on the first semiconductor layer; a fourth semiconductor layer formed on the third semiconductor layer; a gate electrode formed on the fourth semiconductor layer; and a source electrode and a drain electrode formed in contact with the second semiconductor layer. The third semiconductor layer and the fourth semiconductor layer are formed in an area immediately below the gate electrode, the fourth semiconductor layer is formed with a p-type semiconductor material, and the second semiconductor layer and the third semiconductor layer are formed with AlGaN, and the third semiconductor layer has a lower composition ratio of Al than that of the second semiconductor layer.

A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

A Schottky barrier device is provided herein that includes a TMD layer on a substrate, a graphene layer on the TMD layer, an electrolyte layer on the TMD layer, and a source gate contact on the electrolyte layer. A drain contact can be provided on the TMD layer and a source contact can be provided on the graphene layer. As ionic gating from the source gate contact and electrolyte layer is used to adjust the Schottky barrier height this Schottky barrier device can be referred to as an ionic control barrier transistor or ionic barristor.