Provided is a semiconductor device including an active portion and a temperature sensitive portion, the semiconductor including: a semiconductor substrate; and an interlayer dielectric film which is provided above the semiconductor substrate, in which the active portion includes an active trench portion, and an active contact portion, the temperature sensitive portion includes a temperature sensitive diode, and a temperature sensitive contact portion, and a contact width of the temperature sensitive contact portion is larger than a contact width of the active contact portion. Provided is a semiconductor device in which in a depth direction of a semiconductor substrate, an extension depth to which a temperature sensitive trench contact portion extends is shallower than an extension depth to which a plurality of active trench contact portions extend.

A semiconductor device includes a body, a first electrode, and an insulation layer. The body includes: a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type formed at a position where the second semiconductor region is in contact with the first electrode and the insulation layer; and a third semiconductor region of the first conductive type formed in contact with the second semiconductor region such that the third semiconductor region surrounds the second semiconductor region as viewed in a plan view. In the semiconductor device, assuming a total amount of dopants in the second semiconductor region as S1 and a total amount of dopants in the third semiconductor region as S2, a relationship of S1<S2 is satisfied, and a combination of the second semiconductor region and the third semiconductor region has a function of a Zener diode.

A semiconductor device includes a body, a first electrode, and an insulation layer. The body includes: a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type formed at a position where the second semiconductor region is in contact with the first electrode and the insulation layer; and a third semiconductor region of the first conductive type formed in contact with the second semiconductor region such that the third semiconductor region surrounds the second semiconductor region as viewed in a plan view. In the semiconductor device, assuming a total amount of dopants in the second semiconductor region as S1 and a total amount of dopants in the third semiconductor region as S2, a relationship of S1<S2 is satisfied, and a combination of the second semiconductor region and the third semiconductor region has a function of a Zener diode.

A microelectronic device includes at least one capacitor comprising an electrode, a dielectric adjacent to the electrode, and an additional electrode adjacent to the dielectric. The additional electrode is defined by a first portion of a first conductive region. The at least one capacitor also comprises a terminal of a diode adjacent to a second portion of the first conductive region and a portion of a second conductive region. The terminal of a diode is isolated from the electrode. The first conductive region has a different conductivity type than the second conductive region. Also disclosed are a memory device and an integrated circuit device.

A microelectronic device includes at least one capacitor comprising an electrode, a dielectric adjacent to the electrode, and an additional electrode adjacent to the dielectric. The additional electrode is defined by a first portion of a first conductive region. The at least one capacitor also comprises a terminal of a diode adjacent to a second portion of the first conductive region and a portion of a second conductive region. The terminal of a diode is isolated from the electrode. The first conductive region has a different conductivity type than the second conductive region. Also disclosed are a memory device and an integrated circuit device.

A power semiconductor device includes: a main power switch having a drain, source, and gate; and a voltage clamp circuit in parallel with the main power switch and having a clamp voltage less than a breakdown voltage of the main power switch. The voltage clamp circuit includes: a pulldown switch having a normally-on gate electrically connected to the source of the main power switch; a plurality of series-connected diodes electrically connected between the drain of the main power switch and a drain of the pulldown switch; a voltage clamp device electrically connected between a source of the pulldown switch and the source of the main power switch; and a second power switch having a normally-off gate electrically connected to the drain of the pulldown switch, a drain electrically connected to the drain of the main power switch, and a source electrically connected to the source of the pulldown switch.

A power semiconductor device includes: a main power switch having a drain, source, and gate; and a voltage clamp circuit in parallel with the main power switch and having a clamp voltage less than a breakdown voltage of the main power switch. The voltage clamp circuit includes: a pulldown switch having a normally-on gate electrically connected to the source of the main power switch; a plurality of series-connected diodes electrically connected between the drain of the main power switch and a drain of the pulldown switch; a voltage clamp device electrically connected between a source of the pulldown switch and the source of the main power switch; and a second power switch having a normally-off gate electrically connected to the drain of the pulldown switch, a drain electrically connected to the drain of the main power switch, and a source electrically connected to the source of the pulldown switch.

A semiconductor device includes a semiconductor layer over a semiconductor substrate with adjacent first and second portions, the first portion having a first conductivity type, and the second portion having a second, opposite, conductivity type, and an isolation trench extending through first and second portions and laterally surrounding the first and second portions of the semiconductor layer. A method includes implanting dopants of a first conductivity type in a first portion of a semiconductor layer, implanting dopants of a second, opposite, conductivity type in a second portion of the semiconductor layer that is adjacent to the first portion, and forming an isolation trench that extends through and laterally surrounds the first and second portions to form a junction between the interior portions of the first and second portions within the isolation trench that is approximately planar.

A semiconductor device and a manufacturing method of forming the semiconductor device are provided. The semiconductor device includes an active area and a periphery area surrounding the active area, the semiconductor device includes a semiconductor substrate, an epitaxial layer, a field oxide layer, a polysilicon layer, a dielectric layer and a metal contact layer. The semiconductor substrate has a silicon carbide layer. The epitaxial layer is disposed on the semiconductor layer and the epitaxial layer has a doped layer. The polysilicon layer is disposed on the field oxide layer. The polysilicon layer at the periphery area has a plurality of P-plus regions and a plurality of N-plus regions and the plurality of P-plus regions and the plurality of N-plus regions are alternatively arranged to form a zener diode.

A semiconductor device and a manufacturing method of forming the semiconductor device are provided. The semiconductor device includes an active area and a periphery area surrounding the active area, the semiconductor device includes a semiconductor substrate, an epitaxial layer, a field oxide layer, a polysilicon layer, a dielectric layer and a metal contact layer. The semiconductor substrate has a silicon carbide layer. The epitaxial layer is disposed on the semiconductor layer and the epitaxial layer has a doped layer. The polysilicon layer is disposed on the field oxide layer. The polysilicon layer at the periphery area has a plurality of P-plus regions and a plurality of N-plus regions and the plurality of P-plus regions and the plurality of N-plus regions are alternatively arranged to form a zener diode.