The present disclosure relates to a display apparatus and a method for manufacturing the same. A display apparatus including an active layer; a gate electrode disposed on the active layer, an interlayer insulating film on the gate electrode, and a hydrogen-capture layer on the interlayer insulating film. The interlayer insulating film includes a flat surface parallel to an upper surface of the gate electrode and a first inclined surface disposed on one side of the flat surface with a constant slope. The hydrogen-capture layer includes a first hydrogen-capture layer disposed on the flat surface and a second hydrogen-capture layer disposed on the first inclined surface, and the first hydrogen-capture layer and the second hydrogen-capture layer have different crystal structures. This configuration enables control of hydrogen diffusion and carrier concentration, improving hot carrier stress reliability and electrical performance in display devices while supporting efficient manufacturing through selective crystallization during heat treatment.

A transistor and a display apparatus including the same are provided. The display apparatus includes a substrate including an active area and a non-active area. A first transistor is disposed in the active area and includes a first gate electrode, a first-a source drain electrode, a first-b source drain electrode, and a first active layer. A first gate insulation layer is disposed between the first gate electrode and the first active layer. The first gate insulation layer includes a first portion, disposed adjacent to an edge outer portion of the first gate electrode and not overlapping the gate electrode, and a second portion, disposed overlapping the first gate electrode. The thickness of the first portion differs from the thickness of a second portion. By adjusting the gate insulation thickness, the structure may help control dopant distribution and enhance the electrical stability and reliability of the first transistor.

A semiconductor device according to an embodiment of the present invention includes: a first gate electrode; a first gate insulating layer above the first gate electrode; an oxide semiconductor layer above the first gate insulating layer and including a channel portion and a conductive portion; second and third gate insulating layers above the oxide semiconductor layer; and a second gate electrode above the third gate insulating layer, wherein the semiconductor device includes a first region overlapping the channel portion in a plan view and a second region overlapping the conductive portion in the plan view, an amount of impurities included in the conductive portion is more than an amount of the impurities included in the channel portion, the second gate insulating layer in the second region included the impurities, and the third gate insulating layer in the second region does not include the impurities.

A method for forming a semiconductor structure includes alternately forming a plurality of channel layers and a plurality of sacrificial layers over a substrate. The method also includes forming a source/drain trench through the channel layers and the sacrificial layers. The method also includes replacing the sacrificial layers with a plurality of dummy oxide layers. Sidewalls of the dummy oxide layers are substantially aligned with sidewalls of the channel layers. The method also includes selectively forming a plurality of inner spacers on the sidewalls of the dummy oxide layers through the source/drain trench. The method also includes replacing the dummy oxide layers with a gate structure.

A capacitor with large capacitance, a transistor with excellent electrical characteristics, a transistor with high on-state current, or a transistor with small parasitic capacitance is provided. A device includes a first insulating layer, a first conductive layer over the first insulating layer, a second insulating layer over the first insulating layer and the first conductive layer, and a capacitor over the first conductive layer. The second insulating layer includes an opening portion that reaches the first conductive layer and includes a narrowed upper portion. A lower electrode, an upper electrode, and a dielectric of the capacitor each include a portion positioned in the opening portion. The lower electrode includes a portion in contact with the top surface of the first conductive layer and a portion provided along the opening portion.

An example thin-film transistor includes a source, a drain, a gate, and a body of channel material disposed within the influence of the gate between the source and the drain. The body of channel material includes a metal oxide. The body of channel material forms a carrier channel between the source and the drain when sufficient voltage is applied to the gate. The source includes a body of source material that includes ruthenium and an oxide-stabilizing metal that has an oxide that has greater hydrogen stability than ruthenium oxide.

An example thin-film transistor includes a silicon-based substrate and a source and drain at the silicon-based substrate. The source and drain are spaced apart by a gap. The thin-film transistor further includes a nucleation layer in contact with at least the silicon-based substrate within the gap, and a body of channel material in contact with the nucleation layer. The channel material is nanocrystalline tin oxide (SnO.sub.2). The nucleation layer includes a nucleation element that may reduce thermally induced stress between the silicon-based substrate and the body of channel material. The nucleation element may also promote a preferred crystal orientation for the channel material.

An example thin-film transistor includes a source, a drain, a gate, and a body of channel material disposed within the influence of the gate between the source and the drain. The body of channel material includes a metal oxide. The body of channel material forms a carrier channel between the source and the drain when sufficient voltage is applied to the gate. The source includes a body of source material that includes ruthenium and an oxide-stabilizing metal that has an oxide that has greater hydrogen stability than ruthenium oxide.

An oxide semiconductor thin-film transistor includes a gate electrode, a source electrode, a drain electrode, an oxide semiconductor layer connected to the source electrode and the drain electrode, and a gate insulating film between the gate electrode and the oxide semiconductor layer in a layering direction. The oxide semiconductor layer includes a channel region. The gate insulating film includes a metal oxide film and a first insulating film made of silicon nitride and/or silicon oxynitride. A part of the first insulating film is disposed between the metal oxide film and the oxide semiconductor layer. At least a part of a first end of the metal oxide film lies on the channel region and faces either one of the source electrode and the drain electrode in a planar view.

Apparatus and methods are disclosed, including transistors, semiconductor devices and systems. Example semiconductor devices and methods include gate dielectrics in transistor devices with different thicknesses. Apparatus and methods are disclosed using a dopant to vary growth of gate dielectrics at desired locations within a semiconductor device.