A method of manufacturing a thin-film transistor in a display pixel circuit includes forming a gate electrode, forming, a gate insulating layer including a ferroelectric material on the gate electrode, forming a capping layer including a semiconductor layer on the gate insulating layer, and a metal layer on the semiconductor layer, wherein the semiconductor layer includes an oxide semiconductor, configuring the gate insulating layer to exhibit ferroelectricity, through a primary heat treatment process, and forming source/drain electrodes by patterning the metal layer.

A method for forming a semiconductor device structure includes forming fin structures with a stack of alternating first semiconductor layers and second semiconductor layers over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes recessing the first semiconductor layers to form first openings between the second semiconductor layers. The method also includes forming first inner spacers in the first openings. The method also includes removing the fin structures exposed from the gate structure to form a source/drain opening. The method also includes recessing the first semiconductor layers to form second openings between the second semiconductor layers. The method also includes forming second inner spacers in the second openings.

A stacked vertical TFT is provided. Such a stacked vertical TFT may comprise a source electrode, a drain electrode, and a gate electrode between the source electrode and the drain electrode. The source electrode, the gate electrode, and the drain electrode may be arranged on top of one another on vertically separated planes in a stacked arrangement. A semiconductor layer may be provided that at least partially surrounds the stacked arrangement and permits the flow of current carriers from the source to the drain. The source electrode, the gate electrode, and the drain electrode may comprise patterned electrodes. The source electrode, the gate electrode, and the drain electrode comprise identical patterned electrodes. The identical patterned electrodes may be aligned with one another. The patterned electrodes may take the form of perforations or of a comb-like structure.

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate along a first direction, and a gate structure formed over the first nanostructures along a second direction. The semiconductor structure includes an S/D structure formed adjacent to the gate structure, and a dielectric layer formed on the S/D structure. The semiconductor structure includes a plurality of inner spacer layers between the gate structure and the S/D structure. A thickness of a topmost inner spacer layer is greater than a thickness of a bottommost inner spacer layer, and a top surface of the topmost inner spacer layer is higher than a bottom surface of the dielectric layer.

A method for forming a metal oxide layer with high carrier mobility. The method for forming a metal oxide layer includes a first step of forming a first amorphous film, a second step of forming a first crystallized film from the first amorphous film by first heat treatment, a third step of removing a part of the first crystallized film by wet etching to form a seed crystal layer, a fourth step of forming a second amorphous film over the seed crystal layer, and a fifth step of forming a second crystallized film from the second amorphous film by second heat treatment. Each of the first amorphous film, the first crystallized film, the seed crystal layer, the second amorphous film, and the second crystallized film includes indium and oxygen. The first crystallized film includes crystal grains having random orientations. The seed crystal layer has a first crystal orientation with respect to a formation surface. The second crystallized film is formed of crystal grains having the first crystal orientation.