A transistor having high field-effect mobility is provided. A transistor having stable electrical characteristics is provided. A transistor having small current in an off state (in a non-conductive state) is provided. A semiconductor device including such a transistor is provided. A first electrode is formed over a substrate, a first insulating layer is formed adjacent to a side surface of the first electrode, and a second insulating layer is formed to cover the first insulating layer and be in contact with at least part of a surface of the first electrode. The surface of the first electrode is formed of a conductive material that does not easily transmit an impurity element. The second insulating layer is formed of an insulating material that does not easily transmit an impurity element. An oxide semiconductor layer is formed over the first electrode with a third insulating layer provided therebetween.

In one aspect, a method of forming a CMOS device includes forming nanowires suspended over a BOX, wherein a first/second one or more of the nanowires are suspended at a first/second suspension height over the BOX, and wherein the first suspension height is greater than the second suspension height; depositing a conformal gate dielectric on the BOX and around the nanowires wherein the conformal gate dielectric deposited on the BOX is i) in a non-contact position with the conformal gate dielectric deposited around the first one or more of the nanowires, and ii) is in direct physical contact with the conformal gate dielectric deposited around the second one or more of the nanowires such that the BOX serves as an oxygen source during growth of a conformal oxide layer at the interface between the conformal gate dielectric and the second one or more of the nanowires.

A transistor with small parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A semiconductor device including the transistor can be provided. Provided is a transistor including an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor has a first region where the first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween; a second region where the first conductor overlaps with the second conductor with the first and second insulators positioned therebetween; and a third region where the first conductor overlaps with the third conductor with the first and second insulators positioned therebetween. The oxide semiconductor including a fourth region where the oxide semiconductor is in contact with the second conductor; and a fifth region where the oxide semiconductor is in contact with the third conductor.

A light emitting display device includes: a light emitting element; a second transistor connected to a scan line; a first transistor which applies a current to the light emitting element; a capacitor connected to a gate electrode of the first transistor; and a third transistor connected to an output electrode of the first transistor and the gate electrode of the first transistor. Channels of the second transistor, the first transistor, and the third transistor are disposed in a polycrystalline semiconductor layer, and a width of a channel of the third transistor is in a range of about 1 m to about 2 m, and a length of the channel of the third transistor is in a range of about 1 m to about 2.5 m.

A highly reliable semiconductor device with favorable electrical characteristics is provided. A semiconductor device includes a semiconductor layer, an insulating layer, a metal oxide layer, and a conductive layer. The semiconductor layer, the insulating layer, the metal oxide layer, and the conductive layer are stacked in this order. The semiconductor layer includes a first region, a pair of second regions, and a pair of third regions. The first region overlaps the metal oxide layer. The second regions sandwich the first region, overlap the insulating layer, and do not overlap the metal oxide layer. The third regions sandwich the first region and the pair of second regions, and do not overlap the insulating layer. The third region includes a portion having a lower resistance than the first region. The second region includes a portion having a higher resistance than the third region.

The present disclosure provides a semiconductor device and a method for preparing same. The semiconductor device includes a substrate, a source, a semiconductor layer, a drain, an insulating layer, and a gate. A main body portion of the source and a main body portion of the drain are disposed on different faces. The semiconductor layer is disposed between the source and the drain. The gate is disposed on a side of the semiconductor layer. Therefore, a vertical channel thin film transistor (TFT) is formed. In this way, the mobility of carriers in the TFT and the performance of the semiconductor device are effectively improved.

An array substrate, a manufacturing method thereof, and a display panel are provided. The array substrate includes an electrode layer, a gate insulating layer and an active layer. The electrode layer includes a first metal layer, a second metal layer, and a third metal layer that are stacked; a first end of the active layer is electrically connected to the first metal layer, and a second end of the active layer is electrically connected to the third metal layer; in a direction from the first metal layer to the third metal layer, the second metal layer includes at least two metal sub-layers which are stacked, and adjacent ones of the metal sub-layers are insulated from each other. By adjusting thicknesses and a number of the metal sub-layers, a width-to-length ratio of the channel of the active layer can be adjusted to flexibly adjust characteristics of the thin film transistor.

A structure having multi-dielectric layers includes a conduction channel, a sidewall oxide dielectric structure, and a top oxide dielectric structure. The conduction channel contains aluminum. The sidewall oxide dielectric structure is in contact with a side surface of the conduction channel and has a first effective permittivity. The top oxide dielectric structure is in contact with a top surface of the conduction channel and a top surface of the sidewall oxide dielectric structure and has a second effective permittivity. The second effective permittivity is greater than the first effective permittivity.

A structure having multi-dielectric layers includes a conduction channel, a sidewall oxide dielectric structure, and a top oxide dielectric structure. The conduction channel contains aluminum. The sidewall oxide dielectric structure is in contact with a side surface of the conduction channel and has a first effective permittivity. The top oxide dielectric structure is in contact with a top surface of the conduction channel and a top surface of the sidewall oxide dielectric structure and has a second effective permittivity. A material of the top oxide dielectric structure includes silicon. The first effective permittivity is greater than the second effective permittivity.

A semiconductor device may include a substrate including active regions; gate structures including first and second gate structures intersecting first and second active regions, channel layers on the active regions, surrounded by the gate structures; source/drain regions, connected to channel layers, including a first source/drain region in which the first active region is recessed, having a first conductivity-type, and a second source/drain region in which the second active region is recessed, having a second conductivity-type; internal spacers between the first gate structure and the first source/drain region and between the second gate structure and the second source/drain region, each of the first internal spacers including a spacer insulating film between a spacer dielectric layer and the gate structure, and a thickness of the first internal spacers may be greater than a thickness of the second internal spacers.