A non-volatile memory unit and method of manufacturing the same are disclosed. The non-volatile memory unit includes a substrate with a source region and a drain region. A first dielectric layer forms on the substrate. An erase gate, a floating gate and couple control gate are forms on the first dielectric layer. The second dielectric layer and coupled dielectric layer are formed among and above the erase gate, the floating gate and the selective gate, and formed on the couple control gate of the coupled dielectric layer.

A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.

A semiconductor device may include pipe channel layer, and a pipe gate surrounding the pipe channel layer. The semiconductor device may include an oxidization layer formed between the pipe gate and the pipe channel layer. The semiconductor device may include a source side channel layer and a drain side channel layer extended from the pipe channel layer to protrude further than the oxidization layer.

Disclosed is a synaptic transistor, including a substrate, an expansion gate electrode disposed to extend in one direction on the substrate, a gate insulating layer including ions, covering the expansion gate electrode, and disposed on the substrate, a channel layer disposed on the gate insulating layer to correspond to one end of the expansion gate electrode, source and drain electrodes spaced apart from each other, covering both ends of the channel layer, and disposed on the gate insulating layer, and a pad electrode disposed on the gate insulating layer to correspond to the other end of the expansion gate electrode.

A semiconductor device includes a vertical stack of gate electrodes. The gate electrodes extend in different lengths to provide contact regions. The gate electrodes have a conductive region and an insulating region. Contact plugs fills contact holes that pass through the stack of gate electrodes in the contact regions. The contact plugs are connected to the gate electrodes. The contact plugs pass through a conductive region of one gate electrode and are electrically connected to the one gate electrode and pass through the insulating region of other gate electrodes in the contact region. The insulating region is disposed outside of the contact holes in a region in which the gate electrodes intersect the contact plugs.

A voltage detector for detecting whether an input voltage is no lower than a predetermined threshold voltage, includes a reference voltage generator configured to generate a reference voltage, and a comparator configured to receive the input voltage and the reference voltage and to detect whether the input voltage is no lower than the threshold voltage that is determined by the reference voltage. Here, the reference voltage generator includes a first write MOS transistor, a second write MOS transistor, a first output MOS transistor and a second output MOS transistor each including a control gate and a floating gate.

A method to prevent loss of data of transistor-based memory unit including bulk, source and drain formed on bulk and first tunnel oxide, floating gate, second tunnel oxide and control gate stacked up on channel between source and drain is disclosed to include steps of: erasing the floating gate, using weak electric field inject small amount of electrons into floating gate, enabling small amount of electrons to remain in floating gate to keep channel between source and drain electrically conducted, enabling small amount of electrons in floating gate to repel against electrons in first tunnel oxide and second tunnel oxide so as avoid electron accumulation in first tunnel oxide and second tunnel oxide and allow normal data access floating gate, and using electric field of normal write to inject electrons in floating gate so as to prevent channel conduction between source and drain and allow writing data into floating gate.

A single poly nonvolatile memory (NVM) cell includes first and second active regions disposed to face each other and third and fourth active regions spaced apart from the first and second active regions. A drain region, a junction region and a source region are disposed in the fourth active region. A floating gate is disposed on the first and second active regions and is disposed to extend onto the third and fourth active regions. A read/selection gate is disposed to cross the fourth active region between the drain region and the junction region. The first active region is coupled to a first array control gate line, and the second active region is coupled to a second array control gate line. The source region, the junction region and the floating gate constitute a floating gate transistor. The drain region, the junction region and the read/selection gate constitute a read/selection transistor.

The present disclosure relates to a non-volatile memory on a semiconductor substrate, comprising: a first memory cell comprising a floating-gate transistor and a select transistor having an embedded vertical control gate, a second memory cell comprising a floating-gate transistor and a select transistor having the same control gate as the select transistor of the first memory cell, a first bit line coupled to the floating-gate transistor of the first memory cell, and a second bit line coupled to the floating-gate transistor of the second memory cell.

A non-volatile memory unit and method of manufacturing the same are disclosed. The non-volatile memory unit includes a substrate with a source region and a drain region. A first dielectric layer forms on the substrate. An erase gate, a floating gate and couple control gate are forms on the first dielectric layer. The coupled dielectric layer are formed among and above the erase gate, the floating gate and the selective gate, and formed on the couple gate of the coupled dielectric layer.