The present invention provides an amorphous silicon semiconductor TFT backboard structure, which includes a semiconductor layer (4) that has a multi-layer structure including a bottom amorphous silicon layer (41) in contact with a gate insulation layer (3), an N-type heavily-doped amorphous silicon layer (42) in contact with a source electrode (6) and a drain electrode (7), at least two N-type lightly-doped amorphous silicon layers (43) sandwiched between the bottom amorphous silicon layer (41) and the N-type heavily-doped amorphous silicon layer (42), a first intermediate amorphous silicon layer (44) separating every two adjacent ones of the lightly-doped amorphous silicon layers (43), and a second intermediate amorphous silicon layer (45) separating the N-type heavily-doped amorphous silicon layer (42) from the one of the lightly-doped amorphous silicon layers (43) that is closest to the N-type heavily-doped amorphous silicon layer (42). Such a structure further reduces the energy barrier between the drain electrode and the semiconductor layer, making injection of electron easier and ensuring the ON-state current is not lowered down and also helping increase the barrier for transmission of holes, lowering down the leakage current and improving reliability and electrical stability of the TFT.

The present invention provides a LTPS TFT substrate, which includes a black matrix arranged on a first buffer layer of the LTPS TFT substrate to have an area where a TFT device is located is shielded by the black matrix thereby preventing the TFT device from being influenced by light irradiation, maintaining stability of the TFT device; and also saving the manufacturing process of a shielding metal layer, reducing one photo-mask, and lowering down manufacturing cost so as to allow the black matrix, in achieving the functionality of its own (shielding leaking light of the pixel), to also take the place of a shielding metal layer that is commonly adopted in the prior art to shield light for the TFT device and thus providing duality of functionality.

The present disclosure discloses a LTPS TFT and the manufacturing method thereof. The method includes: forming a semiconductor layer and a LTPS layer on the same surface on a base layer; forming an oxide layer is formed on one side of the semiconductor layer facing away the base layer, and forming the oxide layer on one side of the LTPS layer facing away the base layer; forming a first photoresist layer of a first predetermined thickness on the oxide layer; arranging a corresponding first cobalt layer on each of the photoresist layers, a vertical projection of the first cobalt layer overlaps with the vertical projection of the corresponding first photoresist layer; doping high-concentration doping ions into a first specific area of the semiconductor layer. With such configuration, the number of the masking process is decreased and the manufacturing time is reduced.

Disclosed is an electroluminescence device having a substrate, a thin film transistor over the substrate, an insulating film over the thin film transistor, an electroluminescence element over the insulating film, a passivation film over the electroluminescence element, and a counter substrate over the passivation film. The electroluminescence element is configured to emit light through the counter substrate, and a space between the substrate and the counter substrate is filled with a filler. The electroluminescence device is featured by the tapered side surface of a gate electrode of the thin film transistor.

A method for manufacturing an eye-protecting liquid crystal display device is disclosed, in which an ultraviolet light emitting material and a ultraviolet absorbent are added in a first planarization layer of an array substrate and a second planarization layer of a color filter substrate. The ultraviolet absorbent absorbs short-wavelength blue light having a wavelength less than 400 nm and ultraviolet light emitting from a backlight module. The short-wavelength blue light and the ultraviolet light so absorbed excite the ultraviolet light emitting material to give off long-wavelength visible blue light having a wavelength greater than 400 nm. The first and second planarization layers are thus useful in converting ultraviolet light and short-wavelength blue light having a wavelength less than 400 nm, which could damage human eyes, into long-wavelength visible blue light having a wavelength greater than 400 nm that does not damage human eyes.

A method for fabricating a Polysilicon Thin-Film Transistor is provided. The method includes forming a polysilicon active layer, forming a first gate insulation layer and a first gate electrode sequentially on the active layer, conducting a first ion implantation process on the active layer by using the first gate electrode as a mask to form two doped regions at ends of the active layer, forming a second gate insulation layer and a second gate electrode sequentially on the first gate insulation layer and the first gate electrode, and conducting a second ion implantation process on the active layer by using the second gate electrode as another mask to form two source/drain implantation regions at two outer sides of the doped regions of the active layer. Accordingly, impurity concentration of the two doped regions is smaller than that of the two source/drain implantation regions.

There is provided an EL light-emitting device with less uneven brightness. When a drain current of a plurality of current controlling TFTs is Id, a mobility is , a gate capacitance per unit area is Co, a maximum gate voltage is Vgs.sub.(max), a channel width is W, a channel length is L, an average value of a threshold voltage is Vth, a deviation from the average value of the threshold voltage is Vth, and a difference in emission brightness of a plurality of EL elements is within a range of n %, a semiconductor display device is characterized in that

[00001]$A=\frac{2.Math.\mathrm{ID}}{*C_0}$$\frac{A}{{\left({\mathrm{Vgs}}_{\left(\max \right)}-\mathrm{Vth}\right)}^2}\frac{W}{L}{\left(\sqrt{1+\frac{n}{100}}-1\right)}^2*\frac{A}{.Math..Math.{\mathrm{Vth}}^2}$$.Math..Math..Math.\mathrm{Vth}.Math.\left(\sqrt{1+\frac{n}{100}}-1\right)*\sqrt{A*L/W}$

A highly reliable semiconductor device with favorable electrical characteristics is provided. A semiconductor device includes a semiconductor layer, an insulating layer, a metal oxide layer, and a conductive layer. The semiconductor layer, the insulating layer, the metal oxide layer, and the conductive layer are stacked in this order. The semiconductor layer includes a first region, a pair of second regions, and a pair of third regions. The first region overlaps the metal oxide layer. The second regions sandwich the first region, overlap the insulating layer, and do not overlap the metal oxide layer. The third regions sandwich the first region and the pair of second regions, and do not overlap the insulating layer. The third region includes a portion having a lower resistance than the first region. The second region includes a portion having a higher resistance than the third region.

The present application discloses an oxide thin film transistor, a display panel, and a preparation method thereof. Each thickness of the first gate insulating layer of the present application corresponding to the first source doped region, the first drain doped region, the first diffusion region, and the second diffusion region is less than a thickness corresponding to the first channel region; and thicknesses of the first gate insulating layer corresponding to the first diffusion region and the second diffusion region are both different from a thickness corresponding to the first source doped region and the first drain doped region. The the first gate insulating layer effectively shields the first channel region laterally.

The purpose of the present invention is to suppress a change in characteristics of a TFT using an oxide semiconductor film caused by that oxygen in the oxide semiconductor film is extracted by metal electrode. The main structure of the present invention is as follows. A semiconductor device having a TFT, in which a gate insulating film is formed on a gate electrode, and an oxide semiconductor film is formed on the gate insulating film; the oxide semiconductor film including a channel region, a drain region, and a source region; in which a metal nitride film is formed on a top surface of the gate electrode in an opposing portion to the channel region in a plan view; and the metal nitride film is not formed at a part of the top surface of the gate electrode.