An array substrate includes an oxide semiconductor layer; an etch stopper including a first contact hole exposing each of both sides of the oxide semiconductor layer; source and drain electrodes spaced apart from each other with the oxide semiconductor layer therebetween; a first passivation layer including a contact hole exposing each of both ends of the oxide semiconductor layer and each of ends of the source and drain electrode that oppose the both ends of the oxide semiconductor layer, respectively; and a connection pattern at the second contact hole contacting both the oxide semiconductor layer and each of the source and drain electrodes.

A display device manufacturing method includes annealing a display substrate by irradiating a laser to the display substrate in different energy values, measuring a transmittance of the annealed display substrate, and determining an optimal crystallization value of the display substrate based on the transmittance, wherein the determining of the optimal crystallization value includes calculating an absorbance of the display substrate for each energy value of the laser based on the transmittance, calculating a band gap energy of the annealed display substrate for each energy value of the laser based on the absorbance, and determining an energy value of the laser corresponding to a minimum value of the band gap energy as the optimal crystallization value. Also provided is a display device manufacturing apparatus that may implement the manufacturing method.

A semiconductor device having a high degree of integration is provided. The semiconductor device includes a first and a second transistor, and an insulating layer. The first transistor includes a source electrode, a drain electrode over the insulating layer over the source electrode, a first semiconductor layer in contact with a top surface of the source electrode, an inner wall of an opening provided in the insulating layer, and a top surface of the drain electrode, a first gate insulating layer in contact with a top surface and a side surface of the first semiconductor layer, and a first gate electrode over the first gate insulating layer that includes a region overlapping with the inner wall of the opening. The second transistor includes a second semiconductor layer over the insulating layer, the source electrode in contact with one of a top surface and a side surface of the second semiconductor layer, the drain electrode in contact with the other of the top surface and the side surface of the second semiconductor layer, a second gate insulating layer in contact with the top surface of the second semiconductor layer, a top surface and a side surface of the source electrode, and a top surface and a side surface of the drain electrode, and a second gate electrode over the second gate insulating layer. The first semiconductor layer is in contact with the second gate electrode.

A display substrate, a manufacturing method thereof and a display device. The display substrate includes a base substrate and a plurality of subpixels arranged in an array form on the base substrate. Each subpixel includes a voltage stabilizing electrode, and a subpixel driving circuitry including a driving transistor, and a first transistor, a first electrode of which is coupled to a second electrode of the driving transistor, and a second electrode of which is coupled to a gate electrode of the driving transistor. An active layer of the first transistor includes a first semiconductor portion and a second semiconductor portion spaced apart from each other, and a conductor portion coupled to thereto. An orthogonal projection of the conductor portion onto the base substrate overlaps an orthogonal projection of voltage stabilizing electrode of a previous subpixel in the first direction onto the base substrate. According to the present disclosure, it is able to improve the brightness uniformity of the subpixels of a display panel.

An array substrate includes a substrate, a first conductor layer, a protective layer, a gate insulating layer, an active layer, and a second conductor layer. The first conductor layer includes a gate in a thin film transistor area. The protective layer is disposed on the first conductor layer and includes a gate protecting unit on the gate. The gate insulating layer is disposed on the gate protecting unit. The active layer is disposed on the gate insulating layer and in a thin film transistor area. The second conductor layer is disposed on a side of the active layer away from the substrate and includes a source and a drain at intervals in the thin film transistor area.

A display device comprises a substrate including a display area and a pad area adjacent to the display area; at least one pad electrode disposed on the substrate in the pad area and connected to the display area; and at least one dummy electrode overlapping the at least one pad electrode and not connected to the display area.

A display substrate, a manufacturing method thereof and a display device. The display substrate includes a base substrate and a plurality of subpixels arranged in an array form on the base substrate. Each subpixel includes a voltage stabilizing electrode, and a subpixel driving circuitry including a driving transistor, and a first transistor, a first electrode of which is coupled to a second electrode of the driving transistor, and a second electrode of which is coupled to a gate electrode of the driving transistor. An active layer of the first transistor includes a first semiconductor portion and a second semiconductor portion spaced apart from each other, and a conductor portion coupled to thereto. An orthogonal projection of the conductor portion onto the base substrate overlaps an orthogonal projection of voltage stabilizing electrode of a previous subpixel in the first direction onto the base substrate.

A semiconductor device with high aperture ratio is provided. The semiconductor device includes a transistor and a capacitor having a pair of electrodes. An oxide semiconductor layer formed over the same insulating surface is used for a channel formation region of the transistor and one of the electrodes of the capacitor. The other electrode of the capacitor is a transparent conductive film. One electrode of the capacitor is electrically connected to a wiring formed over the insulating surface over which a source electrode or a drain electrode of the transistor is provided, and the other electrode of the capacitor is electrically connected to one of the source electrode and the drain electrode of the transistor.

The present disclosure provides an array substrate and a method of manufacturing the same and a display panel, which belongs to the field of display technologies. The method of manufacturing the array substrate comprises: providing a base substrate; forming a drive circuit layer on the base substrate, wherein the drive circuit layer includes a switching transistor; forming an insulating material layer on one side of the drive circuit layer distal to the base substrate, wherein the insulating material layer has a connection via-hole exposing at least a part region of a drain electrode of the switching transistor; and forming an electrode layer on one side of the insulating material layer distal to the base substrate, wherein a surface of the electrode layer distal to the base substrate has groove structures extending to the connection via-hole.

A bonding apparatus includes a first unit and a second unit. The first unit includes: a first temperature control part, and first fastening holes defined through the first unit and spaced apart from each other in a first direction, where the first unit has a first thermal expansion coefficient. The second unit is disposed under the first unit and is in contact with the first unit. The second unit includes a second temperature control part and second fastening holes defined through the second unit and spaced apart from each other in the first direction, where the second unit has a second thermal expansion coefficient. The bonding apparatus includes fastening members each being inserted into a corresponding first fastening hole and a corresponding second fastening hole, where the corresponding second fastening hole is aligned with the corresponding first fastening hole, and a stage disposed under the second unit.