A method of fabricating a gate stack for a power transistor device includes thermally oxidizing a surface of a Group IIIA-N layer on a substrate to form a first dielectric layer of an oxide material that is >5A thick. A second dielectric layer being silicon nitride or silicon oxynitride is deposited on the first dielectric layer. A metal gate electrode is formed on the second dielectric layer.

In various embodiments of the present disclosure, there is provided a method of manufacturing a monolayer graphene photodetector, the method including forming a graphene quantum dot array in a graphene monolayer, and forming an electron trapping center in the graphene quantum dot array. Accordingly, a monolayer graphene photodetector is also provided.

Atomically layered transition metal dichalcogenides (TMDCs) exhibit a significant potential to enable low-cost transistor biosensors that permit single-molecule-level quantification of biomolecules. Two different principles for operating such biosensors are presented. In one arrangement, antibody receptors are functionalized on an insulating layer deposited onto the channel of the transistor. The charge introduced through antigen-antibody binding is capacitively coupled with the channel and shifts the threshold voltage without significantly changing the transconductance. In another arrangement, antibodies are functionalized directly on the channel of the transistor. Antigen-antibody binding events mainly modulate the ON-state transconductance, which is attributed to the disordered potential formed in channel material.

A change in electrical characteristics of a semiconductor device including an oxide semiconductor is prevented, and the reliability of the semiconductor device is improved. An oxide semiconductor is formed over a substrate; an insulator is formed over the oxide semiconductor; a metal oxide is formed over the insulator; a conductor is formed over the metal oxide; a portion of the oxide semiconductor is exposed by removing the conductor, the metal oxide, and the insulator over the oxide semiconductor; plasma treatment is performed on a surface of the exposed portion of the oxide semiconductor; and a nitride insulator is formed over the exposed portion of the oxide semiconductor and over the conductor. The plasma treatment is performed in a mixed atmosphere of an argon gas and a nitrogen gas.

Semiconductor devices having germanium active layers with underlying diffusion barrier layers are described. For example, a semiconductor device includes a gate electrode stack disposed above a substrate. A germanium active layer is disposed above the substrate, underneath the gate electrode stack. A diffusion barrier layer is disposed above the substrate, below the germanium active layer. A junction leakage suppression layer is disposed above the substrate, below the diffusion barrier layer. Source and drain regions are disposed above the junction leakage suppression layer, on either side of the gate electrode stack.

A manufacturing method of a graphene modulated high-k oxide and metal gate Ge-based MOS device, which comprises the following steps: 1) introducing a graphene thin film on a Ge-based substrate; 2) conducting fluorination treatment to the graphene thin film to form fluorinated graphene; 3) activating the surface of the fluorinated graphene by adopting ozone plasmas, and then forming a high-k gate dielectric on the surface of the fluorinated graphene through an atomic layer deposition technology; and 4) forming a metal electrode on the surface of the high-k gate dielectric. Since the present invention utilizes the graphene as a passivation layer to inhibit the formation of unstable oxide GeO.sub.x on the surface of the Ge-based substrate and to stop mutual diffusion between the gate dielectric and the Ge-based substrate, the interface property between Ge and the high-k gate dielectric layer is improved. The fluorinated graphene can enable the graphene to become a high-quality insulator on the basis of keeping the excellent property of the graphene, so that the influence thereof on the electrical property of the Ge-based device is reduced. By adopting the ozone plasmas to treat the Ge-based graphene and then by adopting the atomic layer deposition technology, an ultrathin Hf-based high-k gate dielectric layer can be obtained.

Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.

The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

A method including forming a barrier layer on a polar compound semiconductor layer on a sacrificial substrate; coupling the sacrificial substrate to a carrier substrate to form a composite structure wherein the barrier layer is disposed between the polar compound semiconductor layer and the carrier substrate; separating the sacrificial substrate from the composite structure to expose the polar compound semiconductor layer; and forming at least one circuit device. An apparatus including a barrier layer on a substrate; a transistor device on the barrier layer; and a polar compound semiconductor layer disposed between the barrier layer and the transistor device, the polar compound semiconductor layer including a two-dimensional electron gas therein.

A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.