A compound semiconductor device includes a carrier supply layer, a channel layer disposed over the carrier supply layer and configured to include InGaAs, and an etching stopper layer disposed over the channel layer, and configured to include a first layer disposed over the channel layer and configured to include In.sub.x1Ga.sub.1-x1P, and a second layer disposed over the first layer and configured to include In.sub.x2Ga.sub.1-x2P, wherein x1 is greater than 0 and less than or equal to 1, x2 is greater than or equal to 0 and less than 1, and x1 is greater than x2.

The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

A semiconductor device includes a first nitride semiconductor layer including gallium, and a second nitride semiconductor layer formed on the first nitride semiconductor layer and including gallium, wherein the second nitride semiconductor layer includes a plurality of third nitride semiconductor layers and a plurality of fourth nitride semiconductor layers alternately laminated on the first nitride semiconductor layer, the plurality of third nitride semiconductor layers include an impurity of a first conductivity type with a first concentration, the plurality of fourth nitride semiconductor layers include the impurity of the first conductivity type with a second concentration higher than the first concentration, and the first concentration is 110.sup.20 cm.sup.3 or higher.

A GaN-based device based on patterned ohmic contact is provided, including: a substrate layer, a nucleation layer, a buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer sequentially disposed in that order from bottom to top. Two ends of the cap layer respectively define ohmic contact recesses extending into the channel layer. A side wall of each ohmic contact recess close to the gate electrode includes multiple arc-shaped side walls and multiple flat side walls. Two epitaxial layers are disposed in the ohmic contact recesses respectively. A passivation layer is covered on the cap layer and the two epitaxial layers, a source electrode and a drain electrode penetrate through the passivation layer and are disposed on the two epitaxial layers respectively. A gate electrode is located between the ohmic contact recesses, and penetrates through the passivation layer and extends to the cap layer.

A GaN-based device based on patterned ohmic contact is provided, including: a substrate layer, a nucleation layer, a buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer sequentially disposed in that order from bottom to top. Two ends of the cap layer respectively define ohmic contact recesses extending into the channel layer. A side wall of each ohmic contact recess close to the gate electrode includes multiple arc-shaped side walls and multiple flat side walls. Two epitaxial layers are disposed in the ohmic contact recesses respectively. A passivation layer is covered on the cap layer and the two epitaxial layers, a source electrode and a drain electrode penetrate through the passivation layer and are disposed on the two epitaxial layers respectively. A gate electrode is located between the ohmic contact recesses, and penetrates through the passivation layer and extends to the cap layer.

A gate (100) for a HEMT (10) to prevent leakage and improve gate stability is configured between the source structure (102-A) and the drain structure (102-B). The gate structure (124) includes a p-type capping layer (108), and a first layer (104) configured with the p-type capping layer (108) to form a Schottky contact with the p-type capping layer (108). The first layer (104) in the gate structure comprises any or the combination of low work function metal or metal alloy such as scandium (Sc) or the tantalum (Ta) or Titanium metal or Titanium Nitride (TiN) or Tantalum Nitride (TaN), with or without gold (Au) to make the Schottky contact with the p-type capping layer (108) in order to suppress gate leakage, improve gate breakdown, and stability to prevent leakage of electric current from the gate structure (124) to the heterojunction structure.

A semiconductor memory device includes a bit line, a channel pattern including a horizontal channel portion on the bit line and a vertical channel portion vertically protruding from the horizontal channel portion, a word line on the horizontal channel portion and on a sidewall of the vertical channel portion, and a gate insulating pattern between the word line and the channel pattern. The channel pattern includes an oxide semiconductor and includes first, second, and third channel layers sequentially stacked. The first to third channel layers include a first metal, and the second channel layer further includes a second metal different from the first metal. At least a portion of the first channel layer contacts the bit line.

Systems and methods for fabricating diamond films are described. One method includes chemically hardening a glass substrate. A nanocrystalline diamond layer may be deposited on the glass substrate via a CV D-based deposition process on at least a first side of the substrate. An ultrananocrystalline diamond layer may be deposited on at least the first side of the substrate.

A method for manufacturing a nitride semiconductor device includes forming an insulating film having a first opening on an upper surface of a first nitride semiconductor layer, the upper surface having a nitrogen polarity, forming a second nitride semiconductor layer on the upper surface inside the first opening, and forming an alignment mark by roughening an upper surface of the second nitride semiconductor layer by a wet etching using an alkaline solution.

This disclosure pertains to a semiconductor device comprising a substrate layer, a buffer layer arranged on the substrate layer, a channel layer arranged on the buffer layer, and a barrier layer forming a two-dimensional electron gas (2DHG) at its interface with the channel layer, a plurality of epitaxial layers arranged on the barrier layer forming a two-dimensional hole gas, a plurality of source terminals, of drain terminals, and a gate terminal arranged over a passivation layer positioned on one of the epitaxial layers, the gate terminal being configured to control electrical conduction in two-dimensional electron gas and in the a two-dimensional hole gas (2DHG).