A semiconductor device may include a substrate, a first transistor and a second transistor positioned on the substrate, a buffer layer disposed between the first transistor and the substrate and between the second transistor and the substrate, a well region positioned within the buffer layer, and an insulating pattern extending through the well region. Each of the first and second transistors may include a channel layer disposed on the substrate, a barrier layer disposed on a corresponding channel layer, a gate electrode positioned on a corresponding barrier layer, and a source electrode and a drain electrode positioned at opposite sides of a corresponding gate electrode and connected to a corresponding channel layer. The source electrode of the first transistor and the drain electrode of the second transistor are connected to the well region.

Field reducing structures for transistor devices having Group III-nitride semiconductor structures are provided. In one example, a transistor device includes a nitrogen-polar (N-polar) Group III-nitride semiconductor structure. The transistor device includes a source contact, a drain contact, and a gate contact. The transistor device includes a field reducing structure operable to reduce an electric field in a region in the N-polar Group III-nitride semiconductor structure between the gate contact and the drain contact.

There is provided a vertical high-electron-mobility transistor, which may include: a drain contact a nanowire layer arranged on the drain contact and at least one vertical nanowire and a supporting material laterally enclosing the at least one vertical nanowire, a heterostructure arranged on the nanowire layer and comprising an AlGaN-layer and a GaN-layer together forming a heterojunction, at least one source contact in contact with the heterostructure, and a gate contact in contact with the heterostructure, arranged above the at least one vertical nanowire, the at least one vertical nanowire is forming an electron transport channel. Also disclosed is a method for producing same.

A high electron mobility transistor (HEMT) heterostructure includes a substrate; a N-polar channel layer; and a N-polar barrier layer positioned between the substrate and the channel layer, wherein the barrier layer comprises a rare-earth III-nitride material. The rare earth III-nitride material can be ScAlN.

A field effect transistor includes a substrate; an electron channel layer disposed on the substrate; a barrier layer disposed on the electron channel layer; a hole channel layer disposed on the barrier layer; a p-type doped semiconductor material layer disposed on the hole channel layer; a source electrode including a first portion in ohmic contact with the electron channel layer and a second portion in ohmic contact with the p-type doped semiconductor material layer; a drain electrode in ohmic contact with the electron channel layer; and a gate electrode disposed facing the p-type doped semiconductor material layer, between the source and drain electrodes.

A semiconductor device includes a first inorganic insulating film covering a first metal layer over a substrate and having a first opening exposing a central area of an upper surface of the first metal layer, a second metal layer on the first metal layer and having a lower surface, a central area of the lower surface contacting the first metal layer through the first opening, a peripheral area of the lower surface contacting the first inorganic insulating film around the first opening, a second inorganic insulating film covering the second metal layer and having a second opening exposing a central area of an upper surface of the second metal layer, and an organic insulating film covering the second inorganic insulating film and having an opening exposing a central area of the upper surface of the second metal layer and overlapping with the second opening when viewed from a thickness direction.