H10F39/1895

Method of wafer-scale integration of semiconductor devices and semiconductor device
09608035 · 2017-03-28 · ·

The method of wafer-scale integration of semiconductor devices comprises the steps of providing a semiconductor wafer (1), a further semiconductor wafer (2), which differs from the first semiconductor wafer in at least one of diameter, thickness and semiconductor material, and a handling wafer (3), arranging the further semiconductor wafer on the handling wafer, and bonding the further semiconductor wafer to the semiconductor wafer. The semiconductor device may comprise an electrically conductive contact layer (6) arranged on the further semiconductor wafer (2) and a metal layer connecting the contact layer with an integrated circuit.

Dual active layer semiconductor device and method of manufacturing the same

Some embodiments include a semiconductor device. The semiconductor device includes a transistor having a gate metal layer, a transistor composite active layer, and one or more contact elements over the transistor composite active layer. The transistor composite active layer includes a first active layer and a second active layer, the first active layer is over the gate metal layer, and the second active layer is over the first active layer. Meanwhile, the semiconductor device also includes one or more semiconductor elements forming a diode over the transistor. The semiconductor element(s) have an N-type layer over the transistor, an I layer over the N-type layer, and a P-type layer over the I layer. Other embodiments of related systems and methods are also disclosed.

Radiation detector, radiation CT apparatus, and method of manufacturing radiation detector
12243903 · 2025-03-04 · ·

A radiation detector in which a semiconductor substrate to convert radiation into charges, a circuit board comprising a readout circuit to read out signals from pixels arranged on the substrate, and a bonding layer to bond the substrate and the circuit board are stacked is provided. Each of the pixels comprises an electrode arranged on a first surface on a side of the circuit board of the substrate. The readout circuit is arranged on a second surface on a side of the substrate of the circuit board, and is connected to a conductive pattern arranged on a third surface on an opposite side of the second surface of the circuit board. The electrode is electrically connected to the readout circuit via the conductive pattern and a second conductive member arranged in a through hole penetrating the circuit board and the bonding layer.

PHOTON COUNTING CONE-BEAM CT APPARATUS WITH MONOLITHIC CMOS INTEGRATED PIXEL DETECTORS
20170055923 · 2017-03-02 ·

CBCT including monolithic photon counting FPD for medical applications requiring real-time 3D imaging, like mammography, interventional guided procedures or external beam radiotherapy, includes CMOS processed readout electronics monolithically integrated with a single crystalline X-ray absorber by covalent wafer bonding near room temperature and adapted for single photon counting providing high energy, temporal and spatial resolution.

X-RAY DETECTOR COMPRISING SCINTILLATOR, WHICH COMPRISES PEROVSKITE COMPOUND
20250113647 · 2025-04-03 · ·

An X-ray detector according to the present disclosure comprises: a scintillator for converting incident X-rays into visible rays; a photoelectric conversion part, which is disposed below the scintillator and converts the visible rays into electrical signals; and a substrate disposed below the photoelectric conversion part, wherein the scintillator comprises a perovskite compound represented by the following chemical formula 1. [Chemical Formula 1] A.sub.3B.sub.2X.sub.5:Activator (In the chemical formula, A is a monovalent metal cation, B is a divalent metal cation, X is a monovalent anion, and the activator is thallium (Tl) or indium (In).)

LIGHT-SENSITIVE MATRIX-ARRAY DETECTOR AND PROCESS FOR PRODUCING THE LIGHTSENSITIVE DETECTOR

A matrix photosensitive detector organized in pixels and to a method for producing the detector, the detector comprising: a flat substrate having multiple interconnect levels connected to one another by through vias, a photodetector grouping together the pixels of the photosensitive detector, arranged on a first external face of the flat substrate and configured to bring about conversion of radiation to which the detector is sensitive into an electrical signal by each of the pixels, semiconductor microcircuits configured to drive and read out each of the pixels, the microcircuits being arranged facing each of the pixels or between adjacent pixels perpendicular to the substrate, each microcircuit being carried on a microsubstrate independent from the flat substrate of the photosensitive detector, the microcircuits being connected individually to the flat substrate at one of its interconnect levels.

Solid-state imaging device

A solid-state imaging device includes a sensor panel section and a readout circuit section. The sensor panel section is disposed on a glass substrate and has a photodetecting section including pixels arrayed in M rows and N columns, row selection lines, and readout lines. The readout circuit section is disposed on a substrate and has N integration circuits. Rectifier circuits are connected between nodes, between N panel-side connection points and the integration circuits, and a constant potential line. Circuit elements having resistance components are connected between the nodes and readout lines.

COMPACT SENSOR MODULE
20170025463 · 2017-01-26 ·

Various embodiments of a compact sensor module are disclosed herein. The sensor module can include a stiffener and a sensor substrate wrapped around a side of the stiffener. A sensor die may mounted on the sensor substrate. A processor substrate may be coupled to the sensor substrate. A processor die may be mounted on the processor substrate and may be in electrical communication with the sensor die.

EDGELESS LARGE AREA ASIC

A three dimensional integrated edgeless pixel detector apparatus can be implemented, which includes a multi-tiered three-dimensional detector having one sensor layer, and two ASIC layers comprising an analog tier and a digital tier configured for x-ray photon time of arrival measurement and Imaging. In a preferred embodiment, a hit processor can be implemented in association with a priority encoder and a configuration register and output serializer with mode selection.

HYBRID PIXEL SENSOR ARRAY
20170006236 · 2017-01-05 ·

A hybrid pixel sensor array is provided. Each pixel of the array comprises: a sensor for generating an imaging signal; a Charged-Coupled Device (CCD) array, coupled to the sensor so as to receive samples from the imaging signal and configured for storage of a plurality of samples; and active CMOS circuitry, coupled to the CCD array for generating a pixel output signal from the stored samples. The sensors of the pixels are part of a sensor portion of the hybrid pixel sensor array that is separate from both the CCD array and active CMOS circuitry of the pixels.