A touch sensor integrated display device includes a plurality of common electrode blocks that defines a plurality of touch driving channels and a plurality of touch sensing channels. The touch driving channel is formed of a group of common electrode blocks electrically linked via a touch signal line placed under the layer of the common electrode blocks. The source/drain of the circuit TFTs provided in the non-display area is formed of the same metal layer of the touch signal line. The source/drain of the pixel TFTs provided in the display area is formed of a metal layer different from the metal layer of the touch signal line.

A semiconductor device includes a conductive resin layer that includes an insulating resin and first fillers dispersed in the insulating resin and has first and second main surfaces, and an element layer that is arranged on the first main surface and includes a semiconductor element. The first fillers are each a fibrous conductive filler. The conductive resin layer has a first surface layer section that includes the first main surface and has a thickness which is 30% of a thickness of the conductive resin layer, a second surface layer section that includes the second main surface and has a thickness which is 30% of the thickness of the conductive resin layer, and an intermediate layer section arranged between the first and second surface layer sections. First fillers have a smaller directional angle relative to the first main surface in the first surface layer section than in the intermediate layer section.

A liquid crystal display panel includes a base substrate, a first step difference compensating pattern, a gate metal pattern, a semiconductor pattern, a source electrode, a drain electrode, a pixel electrode and a color filter. The first step difference compensating pattern is disposed on the base substrate and includes an inorganic material. The gate metal pattern is disposed on the first step difference compensating pattern and includes a gate electrode and a gate line electrically connected to the gate electrode. The semiconductor pattern is overlapped with the gate electrode. The source electrode is electrically connected to the semiconductor pattern. The drain electrode is electrically connected to the semiconductor pattern and is spaced apart from the source electrode. The pixel electrode is electrically connected to the drain electrode. The color filter is overlapped with the pixel electrode.

According to one embodiment, a semiconductor device includes a semiconductor layer including a first semiconductor portion and a second semiconductor portion being continuous with the first semiconductor portion, a first gate electrode, a second gate electrode, an insulating film. The first semiconductor portion includes a first portion, a second portion and a third portion provided between the first portion and the second portion. The second semiconductor portion includes a fourth portion separated from the first portion, a fifth portion separated from the second portion, and a sixth portion provided between the forth portion and the fifth portion. The first gate electrode is separated from the third portion. The second gate electrode is separated from the sixth portion. The insulating film is provided at a first position between the first gate electrode and the semiconductor layer and at a second position between the second gate electrode and the semiconductor layer.

An array substrate includes an oxide semiconductor layer; an etch stopper including a first contact hole exposing each of both sides of the oxide semiconductor layer; source and drain electrodes spaced apart from each other with the oxide semiconductor layer therebetween; a first passivation layer including a contact hole exposing each of both ends of the oxide semiconductor layer and each of ends of the source and drain electrode that oppose the both ends of the oxide semiconductor layer, respectively; and a connection pattern at the second contact hole contacting both the oxide semiconductor layer and each of the source and drain electrodes.

A method of manufacturing a substantially planar electronic device is disclosed. The method employs a resist having three different thicknesses used for defining different structures in a single masking step. Exemplary structures are substantially planar transistors having side-gates and diodes.

A thin film transistor (TFT) substrate which may facilitate subsequent TFT processing by reducing an elevation difference on the top surface of the substrate is disclosed. Aspects include an organic light-emitting apparatus including the TFT substrate, a method of manufacturing the TFT substrate, and a method of manufacturing the organic light-emitting apparatus. In one aspect the TFT substrate includes: a substrate; a height adjusting layer that is disposed on the substrate and has a thickness in a first region greater than a thickness in a second region; and a TFT that is formed on the height adjusting layer to correspond to the second region of the height adjusting layer.

A display device includes: a light emitting element on a substrate; a third-first transistor and a third-second transistor connected in series between a gate electrode of the first transistor and a drain electrode of the first transistor; a first metal layer on the substrate and comprising a gate electrode of the third-first transistor and a gate electrode of the third-second transistor; a hydrogen passivation layer on the first metal layer; a semiconductor region of each of a first transistor, the third-first transistor, and the third-second transistor on the hydrogen passivation layer; a gate electrode on the capping layer; a first bias electrode on a same layer as the gate electrode of the first transistor and overlapping the semiconductor region of the third-first transistor; and a second bias electrode on a same layer as the first bias electrode and overlapping the semiconductor region of the third-second transistor.

The disclosure relates to an array substrate and a manufacturing method thereof, and a display panel. The array substrate includes a plurality of data lines and a plurality of first gate lines, a plurality of first pixel units and a plurality of second pixel units; a plurality of second gate lines; a first TFT and a second TFT, where a first electrode of the first TFT is disposed at one side of the second gate line, the gate and the second electrode of the first TFT is disposed at the other side of the second gate line, the gate, the first electrode, the second electrode and the active layer of each second TFT are disposed at the same side of the second gate line, where the first electrodes of the first TFT and the second TFT are electrically connected to the date lines respectively.

To provide a semiconductor device which can be miniaturized or highly integrated. To obtain a semiconductor device including an oxide semiconductor, which has favorable electrical characteristics. To provide a highly reliable semiconductor device including an oxide semiconductor, by suppression of a change in its electrical characteristics. The semiconductor device includes an island-like oxide semiconductor layer over an insulating surface; an insulating layer surrounding a side surface of the oxide semiconductor layer; a source electrode layer and a drain electrode layer in contact with top surfaces of the oxide semiconductor layer and the insulating layer; a gate electrode layer overlapping with the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode layer. The source electrode layer and the drain electrode layer are provided above the top surface of the oxide semiconductor layer. The top surface of the insulating layer is planarized.