The present invention provides a manufacturing method of a TFT substrate structure, which includes sequentially forming a first passivation layer, a planarization layer, and a first transparent conductive film and then first subjecting the first transparent conductive film to patterning to form a first pixel electrode and thereafter, a photolithographic process is applied to the planarization layer for exposure and thus forming a first via located above and corresponding to a drain terminal, followed by using the planarization layer as a self-aligning mask to apply dry etching to the first passivation layer for etching to form a second via that corresponds to the first via, whereby residues of the first transparent conductive film in the first and second vias can be effectively prevented and product yield is enhanced. Further, on mask can be saved to prevent reduction of aperture ratio caused by misalignment thereby improving the production efficiency, reducing production cost, and increasing cost-related competition power of products.

The present invention provides a manufacturing method of a TFT substrate structure, which includes sequentially forming a first passivation layer, a planarization layer, and a first transparent conductive film and then first subjecting the first transparent conductive film to patterning to form a first pixel electrode and thereafter, a photolithographic process is applied to the planarization layer for exposure and thus forming a first via located above and corresponding to a drain terminal, followed by using the planarization layer as a self-aligning mask to apply dry etching to the first passivation layer for etching to form a second via that corresponds to the first via, whereby residues of the first transparent conductive film in the first and second vias can be effectively prevented and product yield is enhanced. Further, on mask can be saved to prevent reduction of aperture ratio caused by misalignment thereby improving the production efficiency, reducing production cost, and increasing cost-related competition power of products.

An array substrate includes an oxide semiconductor layer; an etch stopper including a first contact hole exposing each of both sides of the oxide semiconductor layer; source and drain electrodes spaced apart from each other with the oxide semiconductor layer therebetween; a first passivation layer including a contact hole exposing each of both ends of the oxide semiconductor layer and each of ends of the source and drain electrode that oppose the both ends of the oxide semiconductor layer, respectively; and a connection pattern at the second contact hole contacting both the oxide semiconductor layer and each of the source and drain electrodes.

A touch sensor integrated display device includes a plurality of common electrode blocks that defines a plurality of touch driving channels and a plurality of touch sensing channels. The touch driving channel is formed of a group of common electrode blocks electrically linked via a touch signal line placed under the layer of the common electrode blocks. The source/drain of the circuit TFTs provided in the non-display area is formed of the same metal layer of the touch signal line. The source/drain of the pixel TFTs provided in the display area is formed of a metal layer different from the metal layer of the touch signal line.

A transistor may be provided by forming, in a forward order or in a reverse order, a gate electrode, a metal oxide liner, a gate dielectric, and an active layer over a substrate, and by forming a source electrode and a drain electrode on end portions of the active layer. The metal oxide liner comprises a thin semiconducting metal oxide material that functions as a hydrogen barrier material.

A transistor may be provided by forming, in a forward order or in a reverse order, a gate electrode, a metal oxide liner, a gate dielectric, and an active layer over a substrate, and by forming a source electrode and a drain electrode on end portions of the active layer. The metal oxide liner comprises a thin semiconducting metal oxide material that functions as a hydrogen barrier material.