According to one embodiment, a semiconductor device includes a plurality of first semiconductor regions of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the first conductivity type, and a gate electrode. An impurity concentration of the second conductivity type of the third semiconductor region is higher than an impurity concentration of the second conductivity type of the second semiconductor regions. The fourth semiconductor region is provided on the first semiconductor regions. The gate electrode provided on the fourth semiconductor region with a gate insulation layer interposed. The gate electrode extends in a third direction. The third direction intersects the first direction. The third direction is parallel to a plane including the first direction and the second direction.

In one general aspect, an apparatus can include a silicon carbide (SiC) device can include a gate dielectric, a first doped region having a first conductivity type, a body region of the first conductivity type, and a second doped region having a second conductivity type. The second doped region has a first portion disposed between the first doped region and the body region, and the second doped region has a second portion disposed between the first doped region and the gate dielectric.

Vertical semiconductor devices with deep wells and associated fabrication methods are disclosed herein. A disclosed process for forming a semiconductor device includes forming, on a drift region having a first conductivity type, a deep well region for the semiconductor device. The deep well region can be formed by an implant. The deep well region has a second conductivity type. The deep well region of the second conductivity type leaves a portion of the surface of the drift region exposed. The process also includes epitaxially forming a semiconductor region that extends from the surface of the drift region to above the deep well region for the semiconductor device. The semiconductor region can be used as at least a part of the main operational current path of the semiconductor device when the semiconductor device is finished and is devoid of implant damage from the implant.

A method for manufacturing a semiconductor device, includes: (a) providing a SiC epitaxial substrate in which on a SiC support substrate, a SiC epitaxial growth layer having an impurity concentration equal to or less than 1/10,000 of that of the SiC support substrate and having a thickness of 50 m or more is disposed; (b) forming an impurity region, which forms a semiconductor element, on a first main surface of the SiC epitaxial substrate by selectively injecting impurity ions; (c) forming an ion implantation region, which controls warpage of the SiC epitaxial substrate, on a second main surface of the SiC epitaxial substrate by injecting predetermined ions; and (d) heating the SiC epitaxial substrate after (b) and (c).

A recess where an edge termination region is lower than an active region is disposed on a silicon carbide base body and an n.sup.-type silicon carbide layer is exposed at a bottom of the recess. In the portion of the n.sup.-type silicon carbide layer exposed at the bottom of the recess, first and second JTE regions configuring a JTE structure are disposed. The first JTE region is disposed from the bottom of the recess, along a side wall and covers a bottom corner portion of the recess. The first JTE region overlaps an outermost first p-type base region at the bottom corner portion. The first JTE region has an impurity concentration that is highest at the portion overlapping the first p-type base region and distribution of the impurity concentration in a depth direction peaks at a portion deeper than the bottom of the recess.

In the silicon carbide semiconductor element, a second silicon carbide semiconductor layer that is in contact with the surface of a first silicon carbide semiconductor layer has at least an upper layer including a dopant of a first conductivity type at a high concentration. Above a junction field effect transistor (JFET) region interposed between body regions that are disposed in the first silicon carbide semiconductor layer so as to be spaced from each other, the silicon carbide semiconductor element has a channel removed region, which is a cutout formed by removing a high concentration layer from the front surface side of the second silicon carbide semiconductor layer, the high concentration layer having a higher dopant concentration than at least the dopant concentration of the JFET region. The width of the channel removed region is smaller than that of the JFET region.

In an active region, p.sup.+ regions are selectively disposed in a surface layer of an n.sup. drift layer on an n.sup.+ semiconductor substrate. A p-base layer is disposed on surfaces of the n.sup. drift layer and the P.sup.+ regions, and an MOS structure is disposed on the p-base layer. In another portion of the active region, a p.sup.+ region is disposed to be in contact with the source electrode on the p.sup.+ regions. In a breakdown voltage structure region (100), a JTE structure having at least a P.sup. region is disposed separately from the P.sup.+ regions and the p-base layer, to surround the active region. The P.sup. region is electrically in contact with the P.sup.+ region in a portion in which the MOS structure is not formed, in the vicinity of the boundary between the active region and the breakdown voltage structure region.

A semiconductor device structure according to some embodiments includes a silicon carbide substrate having a first conductivity type, a silicon carbide drift layer having the first conductivity type on the silicon carbide substrate and having an upper surface opposite the silicon carbide substrate, and a buried junction structure in the silicon carbide drift layer. The buried junction structure has a second conductivity type opposite the first conductivity type and has a junction depth that is greater than about one micron.

An n.sup. drift region is disposed on the front surface of an n.sup.+ semiconductor substrate composed of a wide band gap semiconductor. A p-channel region is selectively disposed on the surface layer of the n.sup. drift region. A high-concentration p.sup.+ base region is disposed so as to adjoin the lower portion of the p-channel region inside the n.sup. drift region. Inside the high-concentration p.sup.+ base region, an n.sup.+ high-concentration region is selectively disposed at the n.sup.+ semiconductor substrate side. The n.sup.+ high-concentration region has a stripe-shaped planar layout extending to the direction that the high-concentration p.sup.+ base regions line up. The n.sup.+ high-concentration region adjoins a JFET region at one end portion in longitudinal direction of the stripe. Further, the n.sup.+ semiconductor substrate side of the n.sup.+ high-concentration region adjoins the part sandwiched between the high-concentration p.sup.+ base region and the n.sup.+ semiconductor substrate in the n.sup. drift region.

The present disclosure provides a semiconductor device, which includes a compensation area which includes p-regions and n-regions, and a plurality of transistor cells on the compensation area. Each of the plurality of transistor cells includes a source region, a body region, a gate and an interlayer dielectric, and a source metallization layer arranged on the interlayer dielectric. The semiconductor device further includes an additional n-doping region that is provided on top of the n-regions between two neighboring body regions, and a source plug which fills a contact hole formed through the interlayer dielectric between the source and body region and the source metallization layer, so as to electrically connect the source and body region and the source metallization layer.