Ferroelectric capacitor is formed by conformably depositing a non-conductive dielectric over the etched first and second electrodes, and forming a metal cap or helmet over a selective part of the non-conductive dielectric, wherein the metal cap conforms to portions of sidewalls of the non-conductive dielectric. The metal cap is formed by applying physical vapor deposition at a grazing angle to selectively deposit a metal mask over the selective part of the non-conductive dielectric. The metal cap can also be formed by applying ion implantation with tuned etch rate. The method further includes isotopically etching the metal cap and the non-conductive dielectric such that non-conductive dielectric remains on sidewalls of the first and second electrodes but not on the third and fourth electrodes.

Some embodiments include a memory cell having a non-ohmic device between a transistor source/drain region and a capacitor. Some embodiments include a memory cell having a transistor with a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. A capacitor is electrically coupled to the second source/drain region through a non-ohmic device. The non-ohmic device includes a non-ohmic-device-material which changes conductivity in response to an electrical property along the channel region. The non-ohmic-device-material has a high-resistivity-mode when the electrical property along the channel region is below a threshold level, and transitions to a low-resistivity-mode when the electrical property along the channel region meets or exceeds the threshold level. Some embodiments include a memory array.

Some embodiments include ferroelectric assemblies. Some embodiments include a capacitor which has ferroelectric insulative material between a first electrode and a second electrode. The capacitor also has a metal oxide between the second electrode and the ferroelectric insulative material. The metal oxide has a thickness of less than or equal to about 30 Å. Some embodiments include a method of forming an assembly. A first capacitor electrode is formed over a semiconductor-containing base. Ferroelectric insulative material is formed over the first electrode. A metal-containing material is formed over the ferroelectric insulative material. The metal-containing material is oxidized to form a metal oxide from the metal-containing material. A second electrode is formed over the metal oxide.

Described is a low power, high-density non-volatile differential memory bit-cell. The transistors of the differential memory bit-cell can be planar or non-planer and can be fabricated in the frontend or backend of a die. A bit-cell of the non-volatile differential memory bit-cell comprises first transistor first non-volatile structure that are controlled to store data of a first value. Another bit-cell of the non-volatile differential memory bit-cell comprises second transistor and second non-volatile structure that are controlled to store data of a second value, wherein the first value is an inverse of the second value. The first and second volatile structures comprise ferroelectric material (e.g., perovskite, hexagonal ferroelectric, improper ferroelectric).

A thin film structure includes a first conductive layer, a dielectric material layer on the first conductive layer, and an upper layer on the dielectric material layer. The dielectric material layer including Hf.sub.xA.sub.1-xO.sub.2 satisfies at least one of a first condition and a second condition. In the first condition the dielectric material layer is formed to a thickness of 5 nm or less and in the second condition the x in Hf.sub.xA.sub.1-xO.sub.2 is in a range of 0.3 to 0.5.

A method used in fabrication of integrated circuitry comprises forming metal material outwardly of a substrate. At least a majority (i.e., up to and including 100%) of the metal material contains ruthenium in at least one of elemental-form, metal compound-form, or alloy-form. A masking material is formed outwardly of the ruthenium-containing metal material. The masking material comprises at least one of nine specifically enumerated materials or category of materials. The masking material is used as a mask while etching through an exposed portion of the ruthenium-containing metal material to form a feature of integrated circuitry that comprises the ruthenium-containing metal material.

A thin film structure including a dielectric material layer, a method of manufacturing the same, and an electronic device employing the same are disclosed. The disclosed thin film structure includes a first conductive layer; a first dielectric material layer on the first conductive layer, the first dielectric material layer having a crystal phase and including a metal oxide; an In.sub.xO.sub.y-based seed material layer formed on the first dielectric material layer and having a thickness less than a thickness of the first dielectric material layer; and a second conductive layer formed on the seed material layer.

A Provided is a semiconductor storage element that includes a memory cell transistor including a gate insulator film at least partially including ferroelectric material, and a selection transistor provided in such a manner that one of a source or a drain is connected with a gate electrode of the memory cell transistor via a connection layer, and a gate insulator film faces the gate insulator film of the memory cell transistor in a layer stack direction across the connection layer.

Methods and devices for reading a memory cell using multi-stage memory sensing are described. The memory cell may be coupled to a digit line after the digit line during a read operation. A transistor may be activated to couple an amplifier capacitor with the digit line during the read operation. The transistor may be deactivated for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled to the digit line. The transistor may be reactivated to recouple the amplifier capacitor to the digit line to help determine the value of the memory cell.

A memory cell comprises channel material, insulative charge-passage material, programmable material, a control gate, and charge-blocking material between the programmable material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material comprising hafnium, zirconium, and oxygen. Other embodiments are disclosed.