An integrated circuit device includes cell transistors at a first vertical level, a front wiring structure at a second vertical level higher than the first vertical level, and a rear wiring structure at a third vertical level lower than the first vertical level. The rear wiring structure includes a device isolation layer arranged on bottom surfaces of the cell transistors, rear contacts arranged in rear contact holes passing through the device isolation layer, a buried interconnector arranged in a recess region that extends into the device isolation layer, connected to a first and second rear contacts, among the rear contacts, and extending in a first horizontal direction or a second horizontal direction, a buried insulating layer arranged in the recess region and arranged on a bottom surface of the buried interconnector, and a rear wiring layer on bottom surfaces of the device isolation layer and the buried insulating layer.

Semiconductor devices include stacked nanosheet channels with inner spacers between respective pairs of the stacked nanosheet channels. Dummy nanosheet remnants are below respective inner spacers, vertically aligned with the respective inner spacers. A source/drain structure is on sidewalls of the plurality of stacked nanosheet channels. A backside contact makes contact with the source/drain structure.

Provided is a semiconductor device including a lower source/drain pattern, a lower channel structure connected to the lower source/drain pattern, a lower gate electrode overlapping the lower channel structure and extending in a first direction, a lower active contact on the lower source/drain pattern, an upper channel structure overlapping the lower channel structure, an upper source/drain pattern connected to the upper channel structure, an upper gate electrode overlapping the upper channel structure and extending in the first direction, an interlayer structure between the lower channel structure and the upper channel structure, and a through active contact extending through the interlayer structure, and electrically connected to the upper source/drain pattern and the lower active contact.

A magnetic memory device includes: a substrate having upper and lower surfaces; a first active region on the upper surface of the substrate, and including a lower channel pattern and a lower source/drain pattern connected to the lower channel pattern; a second active region on the first active region, and including an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern; an interlayer insulating layer covering the lower and upper source/drain patterns; a first active contact on the upper source/drain pattern; an upper insulating layer disposed on the interlayer insulating layer; a first magnetic tunnel junction pattern in the upper insulating layer, and connected to the first active contact; a backside wiring layer on the lower surface of the substrate; a second magnetic tunnel junction pattern in the backside wiring layer; and a second active contact on the lower source/drain pattern.

A semiconductor device includes a power transmission network layer on a first surface of a substrate, a source/drain pattern on the substrate, the source/drain pattern including a first pattern including a first material and a second pattern including a second material that is different from the first material, and a backside conductive contact that extends into the substrate and into the source/drain pattern. The backside conductive contact includes a first region that extends into the first pattern of the source/drain pattern and a second region on the first region. The second region of the backside conductive contact has a second width that is greater than a first width of the first region of the backside conductive contact in a direction parallel to a second surface of the substrate.

A semiconductor storage device including a two-port SRAM cell, in which nanosheets 21 to 24 are formed in line in this order in the X direction, and nanosheets 25 to 28 are formed in line in this order in the X direction. Faces of the nanosheets 21, 23, 25, and 27 on the first side in the X direction are exposed from gate interconnects 30, 33, 35, and 36, respectively. Faces of the nanosheets 22, 24, 26, and 28 on the second side in the X direction are exposed from gate interconnects 33, 34, 36, and 39, respectively.

A method includes forming a multilayer stack, which includes a plurality of semiconductor nanostructures and a plurality of sacrificial layers. The plurality of semiconductor nanostructures and the plurality of sacrificial layers are located alternatingly. The method further includes laterally recessing the plurality of sacrificial layers to form lateral recesses, performing a doping process to dope a first dopant into the lateral recesses, forming inner spacers in the lateral recesses, performing an anneal process to diffuse the first dopant into the inner spacers, and forming a source/drain region contacting the inner spacers, wherein the source/drain region is electrically coupled to the plurality of semiconductor nanostructures.

A semiconductor device includes a substrate comprising a logic cell region and a peripheral region extending around the logic cell region, a logic device in the logic cell region and comprising a plurality of source/drain patterns, an upper active contact on and electrically connected to one of the source/drain patterns, a lower active contact below and electrically connected to another of the source/drain patterns, a conductive structure that penetrates the peripheral region of the substrate, a plurality of peripheral upper wiring lines in the peripheral region and connected to the conductive structure, and a plurality of peripheral lower wiring lines in the peripheral region and connected to the conductive structure opposite the peripheral upper wiring lines. A bottom surface of the conductive structure is lower than a bottom surface of the lower active contact, relative to a bottom surface of the substrate.

Provided are semiconductor devices and methods of fabricating the semiconductor device. The semiconductor device includes a channel, a first source/drain and a second source/drain being apart from each other in a first direction with the channel therebetween, a gate electrode surrounding the channel, an alternating-current wiring line configured to provide alternating current to the channel, and a first conductive contact connecting the alternating-current wiring line and the first source/drain to each other. A height difference from a first surface of the gate electrode facing the alternating-current wiring line to a first surface of the first source/drain in contact with the first conductive contact is less a height difference from a second surface of the gate electrode opposing the first surface of the gate electrode to a second surface of the first source/drain opposing the first surface of the first source/drain.

An integrated circuit device includes an active region extending lengthwise in a first direction on a substrate, a gate structure including a gate line, a high dielectric layer, and an interface dielectric layer, which extend lengthwise in a second direction perpendicular to the first horizontal direction on the active region, a nanosheet arranged on a fin upper surface of the active region and contacting the gate structure, a source/drain region arranged on the active region and contacting the nanosheet, and under the source/drain region in a direction perpendicular to both the first direction and the second direction, a lower insulating spacer arranged in a source/drain recess extending from the fin upper surface of the active region, wherein the interface dielectric layer includes a first portion extending on the nanosheet, and a second portion extending on the source/drain region, and wherein a first thickness of the first portion is different from a second thickness of the second portion.