The present disclosure discloses a gate-all-around field effect transistor which not only can suppress the occurrence of punch through in the substrates and direct leakage of current from the source region/drain region into the part under the channels, but also can facilitate heat release of the substrate, and minimizes the occurrence of device defects due to misalignment between the trench inner spacers and the device by forming trench inner spacers (TISs) and thus preventing source region/drain region impurities from diffusing into the substrate, and a method for manufacturing the same.

A semiconductor integrated circuit device includes transistors that perform differential amplification. Dummy transistors are formed at positions different from the transistors in the depth direction and overlapping the transistors in planar view. Active regions of the transistors are formed line-symmetrically, and active regions of the dummy transistors are also formed line-symmetrically with respect to the same symmetric axis. In the active regions of the dummy transistors, sources and drains at symmetrical positions have the same electrical connection state.

A method includes forming a plurality of semiconductor nanostructures, wherein upper ones of the plurality of semiconductor nanostructures overlap respective lower ones of the plurality of semiconductor nanostructures. A plurality of semiconductor layers are formed, each from one of the plurality of semiconductor nanostructures. The plurality of semiconductor layers are shaped through an etching process. A first semiconductor layer of the plurality of semiconductor layers is etched more than a second semiconductor layer of the plurality of semiconductor layers, wherein the first semiconductor layer is higher than the second semiconductor layer. After the plurality of semiconductor layers are shaped, an additional semiconductor layer is formed to electrically connect to the plurality of semiconductor layers.

A transistor and a method for fabricating the transistor are provided. The semiconductor structure transistor includes a base, a low-dimensional material layer, a plurality of spacers, a source, a drain, and a gate stack. The low-dimensional material layer is provided above the base. The plurality of spacers is provided on a surface of the low-dimensional material layer away from the base and spaced apart from each other. The source and the drain are provided on the surface of the low-dimensional material layer away from the base, respectively. The gate stack is provided on the surface of the low-dimensional material layer away from the base and between the source and the drain, in which the gate stack, the source and the drain are separated by the spacers, and in contact with the spacers, respectively. Therefore, the transistor has advantages of excellent comprehensive performance, high process compatibility, and good device uniformity.

A semiconductor device includes an active pattern including a plurality of channel patterns in a first region, a gate electrode surrounding the channel patterns, a doped bottom pattern including a first well having a first conductivity type and a second well region at the same level as the first well region and having a second conductivity type in a second region, a device isolation layer between the active pattern and the doped bottom pattern, a first doped region in the first well region having a dopant concentration of the first conductivity type larger than that within the first well region, and a second doped region in the second well region having a dopant concentration of the second conductivity type larger than that within the second well region, wherein the first doped region and the second doped region are positioned higher than a bottom surface of the device isolation layer.

A semiconductor integrated circuit device includes first and second transistors constituting a current mirror. The transistors are each constituted by a plurality of units each having an active region. Dummy transistors are each constituted by a plurality of units each having an active region, the plurality of units being placed at positions overlapping the corresponding units of the first and second transistors in planar view. The active regions of the first and second transistors are formed line-symmetrically. The active regions of the dummy transistors are also formed line-symmetrically. In the dummy transistors, sources and drains at symmetric positions have the same electrical connection state.

A semiconductor device includes an active pattern spaced apart in a first direction, and extending in a second direction different from the first direction; a lower channel pattern and a lower source/drain pattern located on the active pattern and alternately arranged in the second direction; an upper channel pattern on the lower channel pattern, and an upper source/drain pattern on the lower source/drain pattern; a gate pattern extending in the first direction and located on the lower channel pattern and the upper channel pattern; a separation pattern located between one of the lower source/drain pattern and the upper source/drain pattern and another of the lower source/drain pattern and the upper source/drain pattern in the second direction; and a gate cutting pattern extending in the second direction across the gate pattern to separate the gate pattern.

An integrated circuit device may include at least one first semiconductor pattern extending in a first horizontal direction, a first source/drain region connected to an end of the at least one first semiconductor pattern in the first horizontal direction, at least one second semiconductor pattern extending in the first horizontal direction and spaced apart from the at least one first semiconductor pattern in a second horizontal direction, a second source/drain region connected to an end of the at least one second semiconductor pattern in the first horizontal direction, and an insulating wall in an insulating wall opening that extends in the first horizontal direction, between the at least one first semiconductor pattern and the at least one second semiconductor pattern and between the first source/drain region and the second source/drain region.

A semiconductor device includes a lower interlayer insulating layer, an insulating pattern extending in a first direction on the lower interlayer insulating layer, a plurality of nanosheets on the insulating pattern and spaced apart in a third direction, an active cut penetrating the lower interlayer insulating layer, the insulating pattern and the plurality of nanosheets, the active cut extending in a second direction and comprising an upper surface extending between opposing first and second sidewalls, and a first gate electrode extending in the second direction on the insulating pattern, wherein the first gate electrode includes a first portion in contact with the first sidewall of the active cut in the second direction, a second portion in contact with the upper surface of the active cut, and a third portion in contact with the second sidewall of the active cut, where the second connects the first portion and the third portion.

A semiconductor device and the method of forming the same are provided. The semiconductor device may include an isolation region, a first dielectric layer over the isolation region, a second dielectric layer over the first dielectric layer, a first source/drain region in the second dielectric layer, a first nanostructure on a sidewall of the first source/drain region, a first gate electrode around the first nanostructure, a first source/drain contact over the first source/drain region electrically connected to the first source/drain region, a conductive feature in the first dielectric layer and the isolation region, and a dielectric feature over the conductive feature and in the second dielectric layer. A first portion of the first source/drain contact may be between two inner sidewalls of the dielectric feature, and the first portion of the first source/drain contact may be electrically connected to the conductive feature.