In an embodiment, a method is described that includes forming a source/drain region having a first base material composition and a first concentration of a first conductivity type dopant; removing a portion of the source/drain region having the first base material composition and the first concentration of the first conductivity type dopant to expose a contact surface; and forming a contact layer on the contact surface. The contact layer comprises a second composition and has a second concentration of the first conductivity type dopant, wherein the second concentration is greater than the first concentration for the first conductivity type dopant. A metal is deposited on the contact layer, wherein an interface between the metal and the contact layer includes a metal semiconductor alloy.

Application of appropriate back bias to a channel of an FET having nanowires or nanosheets is disclosed. In one example, a semiconductor device includes a body electrode extending in a direction perpendicular to a main surface of a substrate; a channel layer extending from a side surface of the body electrode in a first direction parallel to the main surface via an insulating film; a source layer and a drain layer that are in contact with side surfaces of the channel layer in a second direction perpendicular to the first direction and sandwich the channel layer; and a gate electrode provided between the source layer and the drain layer and covering the channel layer with a gate insulating film interposed therebetween.

A semiconductor structure according to the present disclosure includes a semiconductor structure including a backside dielectric layer, a backside etch stop layer (ESL) over the backside dielectric layer, a first source/drain feature and a second source/drain feature over the backside ESL and spaced apart from one another along a first direction, a frontside source/drain contact disposed over the first source/drain feature and the second source/drain feature, a backside contact feature through the backside dielectric layer and the backside ESL to couple to the first source/drain feature, a through via extending through the backside dielectric layer and the backside ESL, a base fin between the backside ESL and the second source/drain feature; and an isolation feature including a portion extending along sidewalls of the base fin. The backside contact feature interfaces the through via in the backside dielectric layer and the isolation feature includes an oxide-based material.

Semiconductor devices and methods of forming the same are provided. An exemplary method includes forming a semiconductor layer stack over a substrate, the semiconductor layer stack having an upper channel layer over a lower channel layer, forming a semiconductor layer, the semiconductor layer comprising a lower portion inducing a compressive strain to the lower channel layer and an upper portion inducing a tensile strain to the upper channel layer, wherein the lower portion is spaced apart from the upper portion, after the forming of the semiconductor layer, forming a first gate structure wrapping around the upper channel layer and a second gate structure wrapping around the lower channel layer, removing the upper portion of the semiconductor layer, and after the forming of the first gate structure and the second gate structure, forming a source/drain feature coupled to the upper channel layer.

Provided is a semiconductor device including a base pattern; channel patterns on an upper surface of the base pattern; a gate structure on the upper surface of the base pattern; a first source/drain pattern on a first side of the gate structure; a second source/drain pattern on a second side of the gate structure; a first source/drain liner between the first source/drain pattern and the gate structure; a second source/drain liner between the second source/drain pattern and the gate structure; and a backside plug in the base pattern, wherein the backside plug is electrically connected to the first source/drain pattern, wherein an upper end of the first source/drain liner is between the first source/drain pattern and the gate structure, and wherein a lower end of the first source/drain liner is between the upper surface of the base pattern and a lower surface of the base pattern.

A method of fabricating a semiconductor device includes forming a first active region and a second active region over a substrate, depositing an isolation structure between the first and second active regions, forming a gate structure across the first active region and the second active region, forming a trench dividing the gate structure into a first segment and a second segment, depositing a dielectric feature in the trench, thinning the substrate and the isolation structure to expose a bottom surface of the dielectric feature, selectively removing a surface layer of the dielectric feature to form an air gap, and depositing a seal layer capping the air gap.

An integrated circuit device may include first and second cell structures on a substrate, a cell boundary between the first and second cell structures in a first direction, a conductive contact overlapping the cell boundary in a second direction, and a conductive track in the second cell structure. The first cell structure may include a first transistor comprising a first sidewall and a second sidewall and a second transistor comprising a third sidewall and a fourth sidewall between an upper surface of the substrate and the first transistor in the second direction. One of the third sidewall and the fourth sidewall may be between the first sidewall and the second sidewall. At least one of the first transistor and the second transistor may be electrically connected to the conductive track through the conductive contact.

An integrated circuit device may include a substrate and a cell structure on an upper surface of the substrate. The cell structure may comprise a first transistor that comprises a first sidewall and a second sidewall that is opposite to the first sidewall in a first direction that is parallel with the upper surface of the substrate and a second transistor that comprises a third sidewall and a fourth sidewall that is opposite to the third sidewall in the first direction between the upper surface of the substrate and the first transistor in a second direction that is perpendicular to the upper surface of the substrate. One of the third sidewall and the fourth sidewall may overlap the first transistor in the second direction.

An integrated circuit device may include a substrate and a cell structure on an upper surface of the substrate. The cell structure may comprise at least a portion of a first transistor that comprises a first sidewall and a second sidewall that is opposite to the first sidewall and at least a portion of a second transistor that comprises a third sidewall and a fourth sidewall that is opposite to the third sidewall between the upper surface of the substrate and the first transistor. One of the third sidewall and the fourth sidewall may overlap the first transistor. The at least the portion of the first transistor may have a first cell width. The at least the portion of the second transistor may have a second cell width. The first cell width may be different from the second cell width.

A semiconductor device includes a substrate, a source electrode on the substrate, a drain electrode being apart from the source electrode, a channel connecting the source electrode to the drain electrode and including a two-dimensional material, a gate insulating layer on the channel, and a gate electrode on the gate insulating layer, wherein the gate electrode includes an overlap area facing the source electrode in a vertical direction.